Apparatuses and method for over-voltage event protection
Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. An example apparatus comprises a thyristor coupled to a node and configured to limit the voltage and discharge the current associated with an over-voltage event at the node. The over-voltage event includes a negative voltage having a magnitude that exceeds a trigger voltage of the thyristor. The example apparatus further comprising a transistor coupled to the thyristor and configured to adjust the magnitude of the trigger voltage.
1. A method comprising:
forming a first well doped with a first dopant type in a bulk material doped with a second dopant type;
forming a first region and a second region each doped with the second dopant type in the first well;
forming a second well doped with the second dopant type in the first well;
forming a third region in the second well doped with the first dopant type;
forming a gate on a surface of the substrate overlapping an area between the first region and the second region; and
connecting the first well and the first region to a common reference node.
2. The method of claim 1 , wherein forming a second well doped with the second dopant type in the first well includes forming the second well adjacent to the first region.
3. The method of claim 1 , further comprising connecting the second well to the second region.
4. The method of claim 1 , further comprising connecting the gate to a trigger voltage source.
5. The method of claim 1 , further comprising connecting the third region to a conductive pad.
6. The method of claim 1 , wherein the first region, the gate, the first well, and the second region together form a transistor, and wherein the first region, the first well, and the second region together form a lateral bi-polar junction transistor, wherein the third region, the second well, the first well, and the second region together form a thyristor.