Decoder unit

1. An apparatus comprising:

an address output circuit configured to output a first address signal comprising a plurality of bits including a first bit section and a second bit section; and

a decoder circuit configured to decode the first address signal to generate a second address signal,

wherein the second address signal indicates a first output value when the first bit section indicates a first input value and a value of the second bit section is in a first value range,

wherein the second address signal indicates a second output value when the first bit section indicates a second input value and a value of the second bit section is in the first value range,

wherein the second address signal indicates a third output value when the first bit section indicates the first input value and a value of the second bit section is in a second value range, and

wherein the second address signal indicates the third output value when the first bit section indicates the second input value and a value of the second bit section is in the second value range.

2. The apparatus of claim 1 ,

wherein the second address signal indicates a fourth output value when the first bit section indicates a third input value and a value of the second bit section is in the first value range, and

wherein the second address signal indicates the third output value when the first bit section indicates the third input value and a value of the second bit section is in the second value range.

3. The apparatus of claim 2 ,

wherein the second address signal indicates a fifth output value when the first bit section indicates a fourth input value and a value of the second bit section is in the first value range, and

wherein the second address signal indicates the third output value when the first bit section indicates the fourth input value and a value of the second bit section is in the second value range.

4. The apparatus of claim 3 ,

wherein the second address signal indicates a sixth output value when the first bit section indicates a fifth input value and a value of the second bit section is in the first value range, and

wherein the second address signal indicates the third output value when the first bit section indicates the fifth input value and a value of the second bit section is in the second value range.

5. The apparatus of claim 4 ,

wherein the second address signal indicates a seventh output value when the first bit section indicates a sixth input value and a value of the second bit section is in the first value range, and

wherein the second address signal indicates the third output value when the first bit section indicates the sixth input value and a value of the second bit section is in the second value range.

6. The apparatus of claim 5 ,

wherein the second address signal indicates an eighth output value when the first bit section indicates a seventh input value and a value of the second bit section is in the first value range, and

wherein the second address signal indicates the third output value when the first bit section indicates the seventh input value and a value of the second bit section is in the second value range.

7. The apparatus of claim 6 ,

wherein the second address signal indicates a ninth output value when the first bit section indicates an eighth input value and a value of the second bit section is in the first value range, and

wherein the second address signal indicates the third output value when the first bit section indicates the eighth input value and a value of the second bit section is in the second value range.

8. The apparatus of claim 7 , wherein the first bit section is 3-bit signal.

9. The apparatus of claim 1 , wherein the second value range is narrower than the first value range.

10. The apparatus of claim 7 , wherein the second value range is smaller than one-eighth of the first value range.

11. The apparatus of claim 10 , wherein the second address signal indicates the third output value when a control signal is activated.

12. The apparatus of claim 11 , wherein the control signal is activated when the first address signal indicates a predetermined value.

13. The apparatus of claim 1 , further comprising a memory cell array divided into a plurality of memory mats,

wherein one of the memory mats is selected based on the second address signal.

14. An apparatus comprising:

an address output circuit configured to output a first address signal comprising a plurality of bits including a first bit section and a second bit section; and

a decoder circuit configured to decode the first address signal to generate a second address signal,

wherein the decoder circuit decides an output value of the second address signal based on the first bit section when a value of the second bit section is in a first value range, and wherein the decoder circuit decides the output value of the second address signal regardless of the first bit section when a value of the second bit section is in a second value range.

15. The apparatus of claim 14 , wherein the second value range is narrower than the first value range.

16. The apparatus of claim 14 ,

wherein the first bit section comprises upper bits of the first address signal, and

wherein the second bit section comprises lower bits of the first address signal.

17. The apparatus of claim 14 , wherein the decoder circuit decides the output value of the second address signal based on a part of the second bit section regardless of a remaining part of the second bit section when the second bit section is in the first value range.

18. The apparatus of claim 14 ,

wherein the decoder circuit brings the output value of the second address signal into a first value when the second bit section is in the second value range, and

wherein the decoder circuit brings the output value of the second address signal into the first value regardless of the first address signal when a control signal is activated.

19. An apparatus comprising:

a memory cell array divided into a plurality of memory mats, each of the memory mat including a plurality of word lines; and

a row control circuit configured to select one of the memory mats and to select one of the word lines in a selected one of the memory mats based on an address signal comprising a plurality of bits including a first bit section, a second bit section, and a third bit section,

wherein the row control circuit selects one of the memory mats based on the first bit section when the second bit section is in a first value range,

wherein the row control circuit selects a predetermined one of the memory mats regardless of the first bit section when the second bit section is in a second value range, and

wherein the row control circuit activates one of the word lines in the selected one of the memory mats based on the first, second, and third bit sections.

20. The apparatus of claim 19 , wherein a number of the memory mats is different from power of two.