IP Library Granted Patent US 10,383,298
Granted Patent B2
US 10,383,298 · App. 16/192,673 · Granted Aug 20, 2019

Apparatus and methods for via connection with reduced via currents

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Quick Facts
Patent No.
US 10,383,298
App. No.
16/192,673
Granted
Aug 20, 2019
Kind
B2
Abstract

Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. The first conductive plate includes a first portion coupled to the first via and the first conductive plate further includes a second portion coupled to the second via between the first portion and the component. The second via is coupled to either the second conductive plate or the third conductive plate.

Claims (49)

1. An apparatus comprising: a printed circuit board (PCB); and an electronic component mounted on the PCB, wherein the PCB comprises: first, second, and third plates; and first through fourth conductive vias, and wherein all four of the first through fourth conductive vias are coupled to the first plate, fewer than four of the first through fourth conductive vias are coupled to the second plate, and fewer than three of the first through fourth conductive vias are coupled to the third plate, wherein further comprising a fourth plate, wherein all four of the first through fourth conductive vias are coupled to the fourth plate.

2. The apparatus of claim 1 , wherein the first through fourth conductive vias are configured to receive, via the fourth plate, a voltage from an external power source and provide the voltage to the first plate.

3. The apparatus of claim 1 , wherein the second plate includes first and second voltage supply regions, and

wherein the second through fourth conductive vias are coupled to the second voltage supply region.

4. The apparatus of claim 3 , wherein the second through fourth conductive vias are configured to receive, via the fourth plate, a voltage from an external power source and provide the voltage to the second voltage supply region of the second plate.

5. The apparatus of claim 1 , wherein the third plate includes third and fourth voltage supply regions, and

wherein the third and fourth conductive vias are coupled to the fourth voltage supply region.

6. The apparatus of claim 5 , wherein the third and fourth conductive vias are configured to receive, via the fourth plate, a voltage from an external power source and provide the voltage to the fourth voltage supply region of the third plate.

7. The apparatus of claim 1 , further comprising fifth and sixth vias,

wherein the third plate includes third and fourth voltage supply regions, and

wherein the fifth and sixth vias are coupled to the third voltage supply region of the third plate.

8. The apparatus of claim 7 , wherein the first through fourth conductive vias are configured to receive, via the fourth plate, a first voltage from an external power source,

wherein the fifth and sixth vias are configured to receive, via the third voltage supply region of the third plate, a second voltage; and

wherein the second voltage is different from the first voltage.

9. The apparatus of claim 8 , wherein the fifth and sixth vias are configured to receive, via the third voltage supply region of the third plate, the second voltage from a ground line.

10. An apparatus comprising:

a printed circuit board (PCB); and

an electronic component mounted on the PCB,

wherein the PCB comprises:

a first plane including a first conductive region;

a second plane including second and third conductive regions;

a third plane including fourth and fifth conductive regions; and

a subset of vias, and

wherein more vias than the subset of vias are coupled to the first conductive region, the subset of vias are coupled to the third conductive region, and fewer vias than the subset of vias are coupled to the fifth conductive region.

11. The apparatus of claim 10 , wherein the subset of vias includes three vias.

12. The apparatus of claim 11 , further comprising a fourth plane,

wherein the subset of vias are coupled to the fourth plane.

13. The apparatus of claim 12 , further comprising a plurality of vias including the subset of vias,

wherein the plurality of vias are coupled to the first and fourth planes, and

wherein a number of the plurality of vias is larger than a number of the subset of vias.

14. The apparatus of claim 12 , wherein the subset of vias include two vias configured to receive, via the fourth plane, a first voltage from an external power source and provide the first voltage to the fifth conductive region of the third plane.

15. The apparatus of claim 12 , further comprising:

a plurality of vias including the subset of vias, and

a plurality of other vias,

wherein the subset of vias are configured to receive, via the fourth plane, a first voltage from an external power source and provide the first voltage to the third conductive region of the second plane, and

wherein the plurality of other vias are configured to receive, via the fourth conductive region of the third plane, a second voltage from a ground line.

16. An apparatus comprising:

a printed circuit board (PCB); and

an electronic component mounted on the PCB,

wherein the PCB comprises:

first through third planes; and

a plurality of vias including a subset of vias,

wherein the subset of vias are coupled to the first through third planes, and

wherein a first via of the plurality of vias is not coupled to the second plane, and a second via of the plurality of vias disposed further from the electronic component than the first via is not coupled to the third plane.

17. The apparatus of claim 16 , wherein the first via is not coupled to the third plane.

18. The apparatus of claim 16 , further comprising a fourth plane,

wherein the plurality of vias are configured to receive, via the fourth plane, a voltage from an external power source and provide the voltage to the first plane.

19. The apparatus of claim 16 , further comprising a fourth plane,

wherein the subset of vias are configured to receive, via the fourth plane, a voltage from an external power source and provide the voltage to the third plane.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051026/0568 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050718/0764 →
SUPPLEMENT NO. 11 TO PATENT SECURITY AGREEMENT Recorded Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048082/0860 →
SUPPLEMENT NO. 2 TO PATENT SECURITY AGREEMENT Recorded Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048082/0889 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 15, 2018
From: MORISHIMA, ATSUSHI
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047519/0468 →