Patent Assignment
Reel/Frame 047784/0014
Assignment of Assignor's Interest
Recorded: 2018-12-14
Pages: 3
Assignors
KABIR, SUTIRTHA
Executed: 2018-12-13
AGARWAL, VISHAL
Executed: 2018-12-13
TAYAL, REENEE RAIZADA
Executed: 2018-12-12
Assignee
CADENCE DESIGN SYSTEMS, INC.
2655 SEELY AVENUE, SAN JOSE, CALIFORNIA, 95134
Covered Property
(1)
Methods for Layout Driven Synthesis of Transmission Line Routes in Integrated Circuits
Patent:
10,706,206 →
Application:
16/220,948 →