Patent Assignment
Reel/Frame 047855/0347
Assignment of Assignor's Interest
Recorded: 2018-12-26
Pages: 3
Assignors
CHENG, JYE-YEN
Executed: 2018-11-02
SHYU, CHEN-YU
Executed: 2018-11-02
LIANG, MING-SHUOH
Executed: 2018-11-02
Assignee
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
NO. 8, LI-HSIN RD. 6, HSINCHU SCIENCE PARK, HSINCHU, 300-78, TAIWAN
Covered Property
(1)
Methods of Fabricating Integrated Circuit Devices Having Reduced Line End Spaces
Patent:
10,522,396 →
Application:
16/174,998 →