Patent Assignment
Reel/Frame 049060/0433
Assignment of Assignor's Interest
Recorded: 2019-05-02
Pages: 4
Assignors
HSIEH, SHANG-CHIH
Executed: 2014-09-26
ZHUANG, HUI-ZHONG
Executed: 2014-09-26
CHIANG, TING-WEI
Executed: 2014-09-26
CHEN, CHUN-FU
Executed: 2014-09-26
TSENG, HSIANG-JEN
Executed: 2014-09-26
Assignee
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
NO. 8, LI-HSIN RD. VI, HSINCHU SCIENCE PARK, HSINCHU, 300, TAIWAN
Covered Property
(1)
System for Designing Integrated Circuit Layout and Method of Making the Integrated Circuit Layout