Patent Assignment
Reel/Frame 049163/0904
Assignment of Assignor's Interest
Recorded: 2019-05-13
Pages: 8
Assignors
TAN, TAT HIN
Executed: 2019-05-08
TEH, CHEE HAK
Executed: 2019-05-08
LOH, TICK SERN
Executed: 2019-05-08
KING, WILFRED WEE KEE
Executed: 2019-05-08
ONG, YU YING
Executed: 2019-05-08
Assignee
INTEL CORPORATION
2200 MISSION COLLEGE BOULEVARD, SANTA CLARA, CALIFORNIA, 94054
Covered Property
(1)
Methods for Mitigating Transistor Aging to Improve Timing Margins for Memory Interface Signals
Related Assignments
(1)
Other recorded transfers of the patent in this record — the chain of ownership.