Patent Assignment
Reel/Frame 072851/0056
Assignment of Assignor's Interest
Recorded: 2025-09-17
Pages: 70
Assignor
INTEL CORPORATION
Executed: 2025-08-19
Assignee
SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
10951 WHITE ROCK ROAD, RANCHO CORDOVA, CALIFORNIA, 95670
Covered Properties
(25)
Methods for Mitigating Transistor Aging to Improve Timing Margins for Memory Interface Signals
Mass Storage System Having Peer-to-Peer Data Movements Between a Cache and a Backend Store
Local Interconnect with Air Gap
Magnetic Memory Device with Ruthenium Diffusion Barrier
Vertically Stacked Memory Elements with Air Gap
Staggered Lines for Interconnect Performance Improvement and Processes for Forming Such
Trenches in Wafer Level Packages for Improvements in Warpage Reliability and Thermals
Wafer Level Passive Heat Spreader Interposer to Enable Improved Thermal Solution for Stacked Dies in Multi-Chips Package and Warpage Control
Semiconductor Die Package with Warpage Management and Process for Forming Such
Integrated Circuit Structures Having Differentiated Interconnect Lines in a Same Dielectric Layer
3D Buildup of Thermally Conductive Layers to Resolve Die Height Differences
Stim/Liquid Metal Filled Laser Drill Trench to Improve Cooling of Stacked Bottom Die
Thermally Conductive Slugs/Active Dies to Improve Cooling of Stacked Bottom Dies
Multi-Chip Module Having a Stacked Logic Chip and Memory Stack
Differential Crosstalk Self-Cancelation in Stackable Structures
High Thermal Conductivity, High Modulus Structure Within a Mold Material Layer of an Integrated Circuit Package
Initialization and Power Fail Isolation of a Memory Module in a System
Coherent Multiprocessing Enabled Compute in Storage and Memory
Storage Transactions with Predictable Latency
Data Scrambler for Persistent Memory
Intermediary for Storage Command Transfers
Controller and Persistent Memory Shared Between Multiple Storage Devices
Techniques to Implement a Hybrid Error Correction Code Scheme
Ferroelectric or Anti-Ferroelectric Trench Capacitor with Spacers for Sidewall Strain Engineering
Offload Defrag Operation for Host-Managed Storage
Related Assignments
(17)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
May 13, 2019
From: TAN, TAT HIN; TEH, CHEE HAK; LOH, TICK SERN; KING, WILFRED WEE KEE
To: INTEL CORPORATION
Reel/Frame 049163/0904 →
Assignment of Assignor's Interest
Jun 4, 2019
From: LIN, KEVIN L; CLENDENNING, SCOTT B.; TRONIC, TRISTAN A.; ALAAN, URUSA
To: INTEL CORPORATION
Reel/Frame 049362/0781 →
Assignment of Assignor's Interest
Jun 19, 2019
From: WALKER, EMILY; NAYLOR, CARL H.; OGUZ, KAAN; LIN, KEVIN L.
To: INTEL CORPORATION
Reel/Frame 049512/0844 →
Assignment of Assignor's Interest
Jun 20, 2019
From: LILAK, AARON D.; MORROW, PATRICK R.; YOO, HUI JAE; MA, SEAN T.
To: INTEL CORPORATION
Reel/Frame 049542/0726 →
Assignment of Assignor's Interest
Jun 28, 2019
From: GRIMSRUD, KNUT S.; TRIKA, SANJEEV N.
To: INTEL CORPORATION
Reel/Frame 049626/0536 →
Assignment of Assignor's Interest
Nov 21, 2019
From: LIN, KEVIN LAI; CHANDHOK, MANISH; RESHOTKO, MIRIAM; JEZEWSKI, CHRISTOPHER
To: INTEL CORPORATION
Reel/Frame 051080/0527 →
Assignment of Assignor's Interest
Nov 25, 2019
From: BRUN, XAVIER F.; MISTRY, KAIZAD; START, PAUL R.; ANANTHAKRISHNAN, NISHA
To: INTEL CORPORATION
Reel/Frame 051111/0012 →
Assignment of Assignor's Interest
Nov 25, 2019
From: MEHTA, VIPUL; BAI, YIQUN; LIN, ZIYIN; DECKER, JOHN
To: INTEL CORPORATION
Reel/Frame 051110/0917 →
Assignment of Assignor's Interest
Nov 25, 2019
From: LIN, ZIYIN; NOFEN, ELIZABETH; MEHTA, VIPUL; GAINES, TAYLOR
To: INTEL CORPORATION
Reel/Frame 051113/0814 →
Assignment of Assignor's Interest
Jan 24, 2020
From: SHARMA, ABHISHEK; YOO, HUI JAE; LE, VAN H.; SUMBUL, HUSEYIN EKIN
To: INTEL CORPORATION
Reel/Frame 051606/0741 →
Assignment of Assignor's Interest
Jan 27, 2020
From: LAJOIE, TRAVIS W.; SHARMA, ABHISHEK A.; ALZATE VINASCO, JUAN G.; KU, CHIEH-JEN
To: INTEL CORPORATION
Reel/Frame 051635/0420 →
Assignment of Assignor's Interest
Feb 22, 2020
From: WAN, ZHIMIN; YANG, JIN; CHIU, CHIA-PIN; LI, PENG
To: INTEL CORPORATION
Reel/Frame 051895/0228 →
Assignment of Assignor's Interest
Feb 22, 2020
From: WAN, ZHIMIN; JHA, CHANDRA MOHAN; CHANG, JE-YOUNG; CHIU, CHIA-PIN
To: INTEL CORPORATION
Reel/Frame 051996/0683 →
Assignment of Assignor's Interest
Feb 22, 2020
From: WAN, ZHIMIN; CHIU, CHIA-PIN; LI, PENG; DEVASENATHIPATHY, SHANKAR
To: INTEL CORPORATION
Reel/Frame 051998/0450 →
Assignment of Assignor's Interest
Mar 2, 2020
From: BAI, YIQUN; MEHTA, VIPUL; DECKER, JOHN; LIN, ZIYIN
To: INTEL CORPORATION
Reel/Frame 052064/0859 →
Assignment of Assignor's Interest
May 7, 2020
From: ZHANG, ZHICHAO; CHEN, ZHE; NEKKANTY, SRIKANT; SRINIVASAN, SRIRAM
To: INTEL CORPORATION
Reel/Frame 052603/0184 →
Assignment of Assignor's Interest
Jun 3, 2020
From: LE, DAT T.; VERGIS, GEORGE
To: INTEL CORPORATION
Reel/Frame 052820/0180 →