Magnetic memory device with ruthenium diffusion barrier
A magnetic memory device comprising a plurality of memory cells is disclosed. The memory device includes an array of memory cells where each memory cell includes a first material layer having a ferromagnetic material, a second material layer having ruthenium, and a third material layer having bismuth and/or antimony. The second material layer is sandwiched between the first material layer and the third material in a stacked configuration.
1. An integrated circuit device, comprising:
an array of memory cells, at least one of the memory cells comprising a first material layer comprising a ferromagnetic material;
a second material layer comprising ruthenium; and
a third material layer comprising bismuth, or antimony, or both bismuth and antimony, wherein the second material layer is sandwiched between the first material layer and the third material layer in a stacked configuration, wherein the third material layer is an insulator layer.
2. The integrated circuit device of claim 1 , wherein the third material layer further comprises selenium.
3. The integrated circuit device of claim 1 , wherein the third material layer further comprises tellurium.
4. The integrated circuit device of claim 1 , wherein the third material layer comprises (Bi 1 ,Sb x ) 2 (Se 1 -yTe y ) 3 , wherein X equals 0 to 1, Y equals 0 to 1, Bi equals bismuth, Sb equals antimony, Se equals selenium, and Te equals tellurium.
5. The integrated circuit device of claim 1 , wherein the ferromagnetic material comprises iron and one or more of nickel, cobalt, and boron.
6. The integrated circuit device of claim 1 , further comprising a magnetoelectric layer on the first material layer.
7. The integrated circuit device of claim 1 , wherein the first material layer is part of a magnetic tunnel junction (MTJ) stack that is above the second material layer.
8. The integrated circuit device of claim 1 , wherein the first material layer and the second material layer have a same cross-sectional area from a top-down perspective.
9. A memory device comprising the integrated circuit device of claim 1 .
10. A processor comprising the integrated circuit device of claim 1 .
11. An electronic device, comprising:
a chip package comprising one or more memory dies, at least one of the one or more memory dies comprising a first material layer comprising a ferromagnetic material;
a second material layer comprising ruthenium; and
a third material layer comprising bismuth or antimony or both bismuth and antimony, wherein the second material layer is sandwiched between the first material layer and the third material layer in a stacked configuration, wherein the third material layer is an insulator layer.
12. The electronic device of claim 11 , wherein the third material layer further comprises selenium or tellurium or both selenium and tellurium.
13. The electronic device of claim 11 , wherein the ferromagnetic material comprises iron and either nickel or cobalt.
14. The electronic device of claim 11 , wherein the first material layer and the second material layer have a same cross-sectional area from a top-down perspective.
15. The electronic device of claim 11 , wherein at least one of the one or more memory dies further comprises a magnetoelectric layer on the first material layer.
16. The electronic device of claim 11 , wherein the first material layer is part of a magnetic tunnel junction (MTJ) stack that is above the second material layer.
17. The electronic device of claim 11 , wherein the third material layer comprises (Bi 1 ,Sb x ) 2 (Se 1 -yTe y ) 3 , wherein X equals 0 to 1, Y equals 0 to 1, Bi equals bismuth, Sb equals antimony, Se equals selenium, and Te equals tellurium.
18. A method of fabricating a memory device, comprising:
depositing a first material layer over a substrate, the first material layer comprising bismuth and/or antimony;
depositing a second material layer over the first material layer, the second material layer comprising ruthenium;
depositing a third material layer over the second material layer, the third material layer comprising a ferromagnetic material;
depositing a stack of layers over the third material layer; etching through a planar thickness of at least the second material layer, the third material layer, and the stack of layers; and
annealing the memory device in a chamber that includes a chalcogen element.
19. The method of claim 18 , wherein the chalcogen element is selenium and/or tellurium.
20. The method of claim 18 , further comprising depositing a capping conductive layer over the stack of layers.
21. The method of claim 18 , wherein the annealing converts the first material layer into a topologically insulating compound.
22. The method of claim 18 , wherein depositing the second material layer comprises depositing the second material layer at a thickness between 0.5 nm and 5 nm.
23. The method of claim 18 , wherein the ferromagnetic material comprises iron and either nickel or cobalt.