IP Library Granted Patent US 12,080,643
Granted Patent B2
US 12,080,643 · App. 16/583,691 · Granted Sep 3, 2024

Integrated circuit structures having differentiated interconnect lines in a same dielectric layer

Inventors: Travis W. Lajoie (Forest Grove, OR); Abhishek A. Sharma (Hillsboro, OR); Juan G. Alzate Vinasco (Tigard, OR); Chieh-Jen Ku (Hillsboro, OR); Shem O. Ogadhoh (Beaverton, OR); Allen B. Gardiner (Portland, OR); Blake C. Lin (Portland, OR); Yih Wang (Portland, OR); Pei-Hua Wang (Beaverton, OR); Jack T. Kavalieros (Portland, OR); Bernhard Sell (Portland, OR); Tahir Ghani (Portland, OR)
Assignee: Intel Corporation
H01L23/5283H01L21/76816H01L21/76829H01L23/5223H01L23/5226
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Quick Facts
Patent No.
US 12,080,643
App. No.
16/583,691
Granted
Sep 3, 2024
Kind
B2
Abstract

Integrated circuit structures having differentiated interconnect lines in a same dielectric layer, and methods of fabricating integrated circuit structures having differentiated interconnect lines in a same dielectric layer, are described. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate. A plurality of conductive interconnect lines is in the ILD layer. The plurality of conductive interconnect lines includes a first interconnect line having a first height, and a second interconnect line immediately laterally adjacent to but spaced apart from the first interconnect line, the second interconnect line having a second height less than the first height.

Claims (29)

1. An integrated circuit structure, comprising:

an inter-layer dielectric (ILD) layer above a substrate; and

a plurality of conductive interconnect lines in the ILD layer, the plurality of conductive interconnect lines comprising:

a first conductive interconnect line; and

a second conductive interconnect line immediately adjacent to the first conductive interconnect line, the second conductive interconnect line having a bottommost surface above a bottommost surface of the first conductive interconnect line, and the second conductive interconnect line having an uppermost surface below an uppermost surface of the first conductive interconnect line, wherein the ILD layer is on the uppermost surface of the second conductive interconnect line,

wherein the second conductive interconnect line has a width less than a width of the first conductive interconnect line.

2. The integrated circuit structure of claim 1 , wherein the uppermost surface of the first conductive interconnect line is co-planar with a top surface of the ILD layer.

3. The integrated circuit structure of claim 1 , further comprising:

an etch stop layer on the ILD layer.

4. The integrated circuit structure of claim 1 , wherein the first conductive interconnect line is defined by a first lithographic process, and the second conductive interconnect line is defined by a second lithographic process.

5. The integrated circuit structure of claim 1 , wherein the first conductive interconnect line has a same composition as the second conductive interconnect line.

6. The integrated circuit structure of claim 1 , wherein the first conductive interconnect line has a different composition than the second conductive interconnect line.

7. A computing device, comprising:

a board; and

a component coupled to the board, the component including an integrated circuit structure, comprising:

an inter-layer dielectric (ILD) layer above a substrate; and

a plurality of conductive interconnect lines in the ILD layer, the plurality of conductive interconnect lines comprising:

a first conductive interconnect line; and

a second conductive interconnect line immediately adjacent to the first conductive interconnect line, the second conductive interconnect line having a bottommost surface above a bottommost surface of the first conductive interconnect line, and the second conductive interconnect line having an uppermost surface below an uppermost surface of the first conductive interconnect line, wherein the ILD layer is on the uppermost surface of the second interconnect line,

wherein the second conductive interconnect line has a width less than a width of the first conductive interconnect line.

8. The computing device of claim 7 , further comprising:

a memory coupled to the board.

9. The computing device of claim 7 , further comprising:

a camera coupled to the board.

10. The computing device of claim 7 , further comprising:

a battery coupled to the board.

11. The computing device of claim 7 , wherein the component is a packaged integrated circuit die.

12. The computing device of claim 7 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

13. The computing device of claim 7 , wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2025
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
Reel/Frame 072851/0056 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2020
From: LAJOIE, TRAVIS W.; SHARMA, ABHISHEK A.; ALZATE VINASCO, JUAN G.; KU, CHIEH-JEN; OGADHOH, SHEM O.; GARDINER, ALLEN B.; LIN, BLAKE C.; WANG, YIH; WANG, PEI-HUA; KAVALIEROS, JACK T.; SELL, BERNHARD; GHANI, TAHIR
To: INTEL CORPORATION
Reel/Frame 051635/0420 →
Continuity (1)
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