IP Library Granted Patent US 11,676,876
Granted Patent B2
US 11,676,876 · App. 16/557,891 · Granted Jun 13, 2023

Semiconductor die package with warpage management and process for forming such

Inventors: Ziyin Lin (Chandler, AZ); Elizabeth Nofen (Phoenix, AZ); Vipul Mehta (Chandler, AZ); Taylor Gaines (Chandler, AZ)
Assignee: Intel Corporation
H01L23/3178H01L21/565H01L21/67288H01L23/367H01L23/373
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Quick Facts
Patent No.
US 11,676,876
App. No.
16/557,891
Granted
Jun 13, 2023
Kind
B2
Abstract

A device is disclosed. The device includes a first die, a plurality of chiplets above the first die, a first underfill material beneath the chiplets, and a gap fill material between the chiplets. The gap fill material is different from the first underfill material. An interface region is formed between the first underfill material and the gap fill material.

Claims (69)

1. A device, comprising:

a first die;

a plurality of chiplets above the first die;

a first underfill material beneath the chiplets;

a gap fill material between the chiplets, the gap fill material different from the first underfill material;

an interface region between the first underfill material and the gap fill material; and

a mold material adjacent sides of the chiplets, wherein the gap fill material is different from the mold material.

2. The device of claim 1 , wherein the gap fill material has a transition temperature of less than 80 degrees Celsius.

3. The device of claim 1 , wherein the gap fill material has a modulus of elasticity that is lower than 6 Gpa.

4. The device of claim 1 , wherein the gap fill has a percent elongation that is greater than 6 percent.

5. The device of claim 1 , further including a second die on a second underfill material.

6. The device of claim 5 , further comprising a thermal interface material above the plurality of chiplets and the second die; and a heat spreader above the thermal interface material and covering the plurality of chiplets and the second die.

7. A system, comprising:

one or more processing components; and

one or more data storage components, at least one of the processing components and the data storage components including at least one semiconductor device, the at least one semiconductor device including:

a first die;

a plurality of chiplets above the first die;

a first underfill material beneath the chiplets;

a mold material adjacent a side of the chiplets; and

a gap fill material between the chiplets, the gap fill material different from the first underfill material; and

an interface region between the first underfill material and the gap fill material.

8. The system of claim 7 , further comprising a mold material adjacent sides of the chiplets, wherein the gap fill material is different from the mold material.

9. The system of claim 7 , wherein the gap fill material has a transition temperature of less than 80 degrees Celsius.

10. The system of claim 7 , wherein the gap fill material has a modulus of elasticity that is less than 6 Gpa.

11. The system of claim 7 , wherein the gap fill has a percent elongation that is greater than 6 percent.

12. The system of claim 7 , further including a second die on a second underfill material.

13. The system of claim 12 , further comprising a thermal interface material above the plurality of chiplets and the second die; and a heat spreader above the thermal interface material and covering the plurality of chiplets and the second die.

14. A method, comprising:

placing a plurality of chiplets above a wafer;

placing an underfill material underneath the plurality of chiplets; and

placing a gap fill material between the plurality of chiplets, the gap fill material different from the underfill material, wherein an interface region is formed between the underfill material and the gap fill material, wherein the gap fill material is formed between the plurality of chiplets before the underfill material is placed underneath the plurality of chiplets.

15. The method of claim 14 , wherein the underfill material is placed on the wafer before the chiplets are placed above the wafer.

16. The method of claim 14 , wherein the underfill material is placed on the wafer after the chiplets are placed above the wafer.

17. The method of claim 14 , wherein the gap fill material has a transition temperature of less than 80 degrees Celsius.

18. The method of claim 14 , wherein the gap fill material has a modulus of elasticity that is less than 6 Gpa.

19. The method of claim 14 , wherein the gap fill has a percent elongation that is greater than 6 percent.

20. A method, comprising:

providing a first die;

placing a plurality of chiplets above the first die;

forming a first underfill material beneath the chiplets;

forming a gap fill material between the chiplets, the gap fill material different from the first underfill material, wherein an interface region is formed between the first underfill material and the gap fill material; and

forming a mold material adjacent the sides of the chiplets wherein the gap fill material is different from the mold material.

21. The method of claim 20 , wherein the gap fill material has a transition temperature of less than 80 degrees Celsius.

22. The method of claim 20 , wherein the gap fill material has a modulus of elasticity that is less than 6 Gpa.

23. A device, comprising:

a first die;

a plurality of chiplets above the first die;

a first underfill material beneath the chiplets;

a gap fill material between the chiplets, the gap fill material different from the first underfill material, wherein the gap fill material has a transition temperature of less than 80 degrees Celsius; and

an interface region between the first underfill material and the gap fill material.

24. A device, comprising:

a first die;

a plurality of chiplets above the first die;

a first underfill material beneath the chiplets;

a gap fill material between the chiplets, the gap fill material different from the first underfill material, wherein the gap fill material has a modulus of elasticity that is lower than 6 Gpa; and

an interface region between the first underfill material and the gap fill material.

25. A device, comprising:

a first die;

a plurality of chiplets above the first die;

a first underfill material beneath the chiplets;

a gap fill material between the chiplets, the gap fill material different from the first underfill material, wherein the gap fill has a percent elongation that is greater than 6 percent; and

an interface region between the first underfill material and the gap fill material.

26. A device, comprising:

a first die;

a plurality of chiplets above the first die;

a first underfill material beneath the chiplets;

a gap fill material between the chiplets, the gap fill material different from the first underfill material;

an interface region between the first underfill material and the gap fill material; and

a second die on a second underfill material.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2025
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
Reel/Frame 072851/0056 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 25, 2019
From: LIN, ZIYIN; NOFEN, ELIZABETH; MEHTA, VIPUL; GAINES, TAYLOR
To: INTEL CORPORATION
Reel/Frame 051113/0814 →
Continuity (1)
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