IP Library Assignment 049835/0589
Patent Assignment
Reel/Frame 049835/0589

Assignment of Assignor's Interest

Recorded: 2019-07-23 Pages: 6
Assignor
FREESCALE SEMICONDUCTOR, INC.
Executed: 2011-07-29
Assignee
RAMBUS INC.
1050 ENTERPRISE WAY, SUITE 700, SUNNYVALE, CALIFORNIA, 94089
Covered Properties (3)
Executing Misaligned Load Dependent Instruction in Second Execution Stage in Parity Protected Mode in Configurable Pipelined Processor
Patent: 8,364,937 →
Application: 13/446,930 →
Publication: US 2012/0204012
Processor executing instructions in ALU in first / second pipeline stage during non-ECC / ECC mode
Patent: 9,135,010 →
Application: 13/750,345 →
Publication: US 2013/0246750
Configurable Pipeline Based on Error Detection Mode in a Data Processing System
Application: 16/026,733 →
Publication: US 2019/0065207
Related Assignments (1)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Jul 23, 2019
From: MOYER, WILLIAM C; SCOTT, JEFFREY W
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 049840/0745 →