Patent Assignment
Reel/Frame 049950/0517
Confirmatory Patent Assignment
Recorded: 2019-04-17
Pages: 7
Assignor
ABDALLAH, MOHAMMAD
Executed: 2016-08-12
Assignee
SOFT MACHINES, INC.
3920 FREEDOM CIRCLE, SANTA CLARA, CALIFORNIA, 95054
Covered Properties
(35)
Fast Unaligned Memory Access
Cache Replacement Policy
Guest to Native Block Address Mappings and Management of Native Code Storage
Application:
61/436,957 →
Variable Caching Structure for Managing Physical Storage
Application:
61/436,959 →
Hardware Acceleration Components for Translating Guest Instructions to Native Instructions
Application:
61/436,966 →
Multilevel Conversion Table Cache for Translating Guest Instructions to Native Instructions
Application:
61/436,973 →
Guest Instruction Block with Near Branching and Far Branching Sequence Constrution to Native Instruction Block
Application:
61/436,975 →
Register File Segments for Supporting Code Block Execution by Using Virtual Cores Instantiated by Partitionable Engines
Application:
61/467,939 →
Memory Fragments for Supporting Code Block Execution by Using Virtual Cores Instantiated by Partitionable Engines
Application:
61/467,940 →
Executing Instruction Sequence Code Blocks by Using Virtual Cores Instantiated by Partitionable Engines
Application:
61/467,944 →
Decentrallized Allocation of Resources and Interconnnect Structures to Support the Execution of Instruction Sequences by a Plurality of Engines
Application:
61/488,662 →
Interconnect Structure to Support the Execution of Instruction Sequences by a Plurality of Engines
Application:
61/488,683 →
Method and Apparatus to Allow Early Dependency Resolution and Data Forwarding in a Microprocessor
Application:
61/792,676 →
Method and Apparatus for Nearest Potential Store Tagging
Application:
61/792,885 →
Method and Apparatus for Guest Return Address Stack Emulation Supporting Speculation
Application:
61/793,174 →
Method and Apparatus for Predicting the Way of Set Associative Shadow Cache
Application:
61/793,703 →
Method and Apparatus for Sorting Elements in Hardware Structures
Application:
61/793,752 →
Method for Populating a Source View Data Structure by Using Register Template Snapshots
Application:
61/798,988 →
Method for Populating Register View Data Structure by Using Register Template Snapshots
Application:
61/799,006 →
Method and Apparatus to Speed Up the Load Access and Data Return Speed Path Using Early Calculated Lower Address Bits
Application:
61/799,116 →
Method for Populating and Instruction View Data Structure by Using Register Template Snapshots
Application:
61/799,299 →
Method for Dependency Broadcasting Through a Source Organized Source View Data Structure
Application:
61/799,407 →
Method for Dependency Broadcasting Through a Block Organized Source View Data Structure
Application:
61/799,530 →
Method and Apparatus for a Wide and Efficient Front-End to Emulate a Guest-Architecture
Application:
61/799,717 →
Method for Implementing a Reduced Size Register View Data Structure in a Microprocessor
Application:
61/799,736 →
Method for Implementing a Reduced Size Register View Data Structure in a Microprocessor
Application:
61/799,892 →
Method for Executing Blocks of Instructions Using a Microprocessor Architecture Having a Register View, Source View, Instruction View, and a Plurality of Register Templates
Application:
61/799,902 →
Method for Executing Multithreaded Instructions Grouped into Blocks
Application:
61/800,123 →
Method for Performing Dual Dispatch of Blocks and Half Blocks
Application:
61/800,179 →
Method for Emulating a Guest Centralized Flag Architecture by Using a Native Stupid Flag Architecture
Application:
61/800,487 →
Method for a delayed branch implementation by using a front end track table
Application:
61/852,057 →
Method for a staged optimized high-speed adder
Application:
61/852,338 →
Method for implementing a line speed interconnect structure
Application:
61/852,389 →
Method and Apparatus for Providing Hardware Support for Self-Modifying Code
Application:
61/991,951 →
Runtime Architecture for Efficiently Optimizing and Executing Guest Code and Converting to Native Code
Application:
62/029,383 →
Related Assignments
(2)
Other recorded transfers of the patents in this record — the chain of ownership.