IP Library › Assignment 040631/0915
Patent Assignment
Reel/Frame 040631/0915

Assignment of Assignor's Interest

Recorded: 2016-11-14 Pages: 61
Assignor
SOFT MACHINES, INC.
Executed: 2016-11-07
Assignee
INTEL CORPORATION
2200 MISSION COLLEGE BOULEVARD, SANTA CLARA, CALIFORNIA, 95054
Covered Properties (217)
Methods and Systems for Managing Synonyms in Virtually Indexed Physically Tagged Caches
Guest Instruction to Native Instruction Range Based Mapping Using a Conversion Look Aside Buffer of a Processor
Guest Instruction Block with Near Branching and Far Branching Sequence Construction to Native Instruction Block
Multilevel Conversion Table Cache for Translating Guest Instructions to Native Instructions
Hardware Acceleration Components for Translating Guest Instructions to Native Instructions
Guest to Native Block Address Mappings and Management of Native Code Storage
Variable Caching Structure for Managing Physical Storage
Executing Instruction Sequence Code Blocks by Using Virtual Cores Instantiated Bt Partitionable Engines
Register File Segments for Supporting Code Block Execution by Using Virtual Cores Instantiated by Partitionable Engines
Memory Fragments for Supporting Code Block Execution by Using Virtual Cores Instantiated by Partitionable Engines
Decentralized Allocation of Resources and Interconnect Structures to Support the Execution of Instruction Sequences by a Plurality of Engines
An Interconnect Structure to Support the Execution of Instruction Sequences by a Plurality of Engines
Systems and Methods for Accessing a Unified Translation Lookaside Buffer
Reordered Speculative Instruction Sequences with a Disambiguation-Free Out of Order Load Store Queue
A Load Store Buffer Agnostic to Threads Implementing Forwarding from Different Threads Based on Store Seniority
A Method and System for Filtering the Stores to Prevent All Stores from Having to Snoop Check Against All Words of a Cache
A Virtual Load Store Queue Having a Dynamic Dispatch Window with a Distributed Structure
A Semaphore Method and System with Out of Order Loads in a Memory Consistency Model That Constitutes Loads Reading from Memory in Order
A Lock-Based and Synch-Based Method for Out of Order Loads in a Memory Consistency Model Using Shared Memory Resources
An Instruction Definition to Implement Load Store Reordering and Optimization
A Method and System for Implementing Recovery from Speculative Forwarding Miss-Predictions/Errors Resulting from Load Store Reordering and Optimization
A Virtual Load Store Queue Having a Dynamic Dispatch Window with a Unified Structure
A Disambiguation-Free Out of Order Load Store Queue
Systems and Methods for Supporting a Plurality of Load Accesses of a Cache in a Single Cycle
A Method for Populating Register View Data Structure by Using Register Template Snapshots
A Method for Executing Blocks of Instructions Using a Microprocessor Architecture Having a Register View, Source View, Instruction View, and a Plurality of Register Templates
A Method for Dependency Broadcasting Through a Block Organized Source View Data Structure
A Method for Implementing a Reduced Size Register View Data Structure in a Microprocessor
A Method for Executing Multithreaded Instructions Grouped Onto Blocks
A Method for Emulating a Guest Centralized Flag Architecture by Using a Native Distributed Flag Architecture
Method and Apparatus to Allow Early Dependency Resolution and Data Forwarding in a Microprocessor
Method and Apparatus for Guest Return Address Stack Emulation Supporting Speculation
Method and Apparatus for Sorting Elements in Hardware Structures
A Method for Implementing a Line Speed Interconnect Structure
Method and Apparatus to Avoid Deadlock During Instruction Scheduling Using Dynamic Port Remapping
Method and Apparatus for Efficient Scheduling for Asymmetrical Execution Units
Using a Plurality of Conversion Tables to Implement an Instruction Set Agnostic Runtime Architecture
System for an Instruction Set Agnostic Runtime Architecture
Using a Conversion Look Aside Buffer to Implement an Instruction Set Agnostic Runtime Architecture
An Allocation and Issue Stage for Reordering a Microinstruction Sequence into an Optimized Microinstruction Sequence to Implement an Instruction Set Agnostic Runtime Architecture
A System Converter That Executes a Just in Time Optimizer for Excuting Code from a Guest Image
A System Converter That Implements a Reordering Process Through Jit (Just in Time) Optimization That Ensures Loads Do Not Dispatch Ahead of Other Loads That Are to the Same Address
A System Coneverter That Implements a Run Ahead Run Time Guest Instruction Conversion/Decoding Process and a Prefetching Process Where Guest Code Is Pre-Fetched from the Target of Guest Branches in an Instruction Sequence
Plural Matrices of Execution Units for Processing Matrices of Row Dependent Instructions in Single Clock Cycle in Super or Separate Mode
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Parallel Processing of a Sequential Program Using Hardware Generated Threads and Their Instruction Groups Executing on Plural Execution Units and Accessing Register File Segments Using Dependency Inheritance Vectors Across Multiple Engines
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Guest Instruction to Native Instruction Range Based Mapping Using a Conversion Look Aside Buffer of a Processor
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Publication: US 2012/0198157
Guest Instruction Block with Near Branching and Far Branching Sequence Construction to Native Instruction Block
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Guest to Native Block Address Mappings and Management of Native Code Storage
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Variable Caching Structure for Managing Physical Storage
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Multilevel Conversion Table Cache for Translating Guest Instructions to Native Instructions
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Mapping of guest instruction block assembled according to branch prediction to translated native conversion block
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Systems and Methods for Accessing a Unified Translation Lookaside Buffer
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Register File Segments for Supporting Code Block Execution by Using Virtual Cores Instantiated by Partitionable Engines
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Executing Instruction Sequence Code Blocks by Using Virtual Cores Instantiated by Partitionable Engines
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Memory Fragments for Supporting Code Block Execution by Using Virtual Cores Instantiated by Partitionable Engines
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Decentralized Allocation of Resources and Interconnect Structures to Support the Execution of Instruction Sequences by a Plurality of Engines
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Global and Local Interconnect Structure Comprising Routing Matrix to Support the Execution of Instruction Sequences by a Plurality of Engines
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Systems and Methods for Maintaining the Coherency of a Store Coalescing Cache and a Load Cache
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Systems and Methods for Flushing a Cache with Modified Data
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Systems and Methods for Supporting a Plurality of Load Accesses of a Cache in a Single Cycle
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Systems and Methods for Supporting a Plurality of Load and Store Accesses of a Cache
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Systems and Methods for Implementing Weak Stream Software Data and Instruction Prefetching Using a Hardware Data Prefetcher
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Systems and Methods for Load Canceling in a Processor That Is Connected to an External Interconnect Fabric
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Systems and Methods for Non-Blocking Implementation of Cache Flush Instructions
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Processor executing super instruction matrix with register file configurable for single or multiple threads operations
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Single Cycle Multi-Branch Prediction Including Shadow Cache for Early Far Branch Prediction
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Instruction Sequence Buffer to Enhance Branch Prediction Efficiency
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Instruction Sequence Buffer to Store Branches Having Reliably Predictable Instruction Sequences
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Publication: US 2014/0075168
Systems and Methods for Acquiring Data for Loads at Different Access Times from Hierarchical Sources Using a Load Queue as a Temporary Storage Buffer and Completing the Load Early
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Systems and Methods for Read Request Bypassing a Last Level Cache That Interfaces with an External Fabric
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Systems and Methods for Invasive Debug of a Processor Without Processor Execution of Instructions
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Systems and Methods for Faster Read After Write Forwarding Using a Virtual Address
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Publication: US 2015/0067230
Method and Apparatus for Sorting Elements in Hardware Structures
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Publication: US 2014/0281422
Microprocessor for Gating a Load Operation Based on Entries of a Prediction Table
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Publication: US 2014/0281408
Apparatus for Gating a Load Operation Based on Entries of a Prediction Table
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Publication: US 2014/0281384
Method and Apparatus to Avoid Deadlock During Instruction Scheduling Using Dynamic Port Remapping
Patent: 9,582,322 →
Application: 14/101,615 →
Publication: US 2014/0282575
Method and Apparatus for Efficient Scheduling for Asymmetrical Execution Units
Patent: 9,632,825 →
Application: 14/107,116 →
Publication: US 2014/0373022
Method and Apparatus for Supporting a Plurality of Load Accesses of a Cache in a Single Cycle to Maintain Throughput
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Application: 14/173,602 →
Publication: US 2014/0156947
Method and Apparatus for Preventing Non-Temporal Entries from Polluting Small Structures Using a Transient Buffer
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Publication: US 2014/0317351
Cache Storing Data Fetched by Address Calculating Load Instruction with Label Used as Associated Name for Consuming Instruction to Refer
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Publication: US 2014/0181475
Method and Apparatus for Nearest Potential Store Tagging
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Publication: US 2014/0281409
Method and Apparatus to Allow Early Dependency Resolution and Data Forwarding in a Microprocessor
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Publication: US 2014/0281410
Method and Apparatus for Guest Return Address Stack Emulation Supporting Speculation
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Publication: US 2014/0281388
Method and Apparatus to Speed up the Load Access and Data Return Speed Path Using Early Lower Address Bits
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Publication: US 2014/0281116
Method for Using Register Templates to Track Interdependencies Among Blocks of Instructions
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Publication: US 2015/0046683
Method for Executing Blocks of Instructions Using a Microprocessor Architecture Having a Register View, Source View, Instruction View, and a Plurality of Register Templates
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Method for Populating a Source View Data Structure by Using Register Template Snapshots
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Publication: US 2014/0281426
Method for Dependency Broadcasting Through a Source Organized Source View Data Structure
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Publication: US 2014/0281411
Method for Performing Dual Dispatch of Blocks and Half Blocks
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Publication: US 2014/0317387
Method for Implementing a Reduced Size Register View Data Structure in a Microprocessor
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Publication: US 2014/0281427
Method for Emulating a Guest Centralized Flag Architecture by Using a Native Distributed Flag Architecture
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Publication: US 2014/0281436
Method for Populating Register View Data Structure by Using Register Template Snapshots
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Publication: US 2014/0281428
Method for Implementing a Line Speed Interconnect Structure
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Publication: US 2014/0269753
Method for Populating and Instruction View Data Structure by Using Register Template Snapshots
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Publication: US 2014/0281412
Method for a Stage Optimized High Speed Adder
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Publication: US 2014/0324937
Method for Implementing a Reduced Size Register View Data Structure in a Microprocessor
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Publication: US 2014/0281416
Method for Executing Multithreaded Instructions Grouped into Blocks
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Publication: US 2014/0282592
Methods, Systems and Apparatus for Predicting the Way of a Set Associative Cache
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Publication: US 2014/0281242
Methods, Systems and Apparatus for Supporting Wide and Efficient Front-End Operation with Guest-Architecture Emulation
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Publication: US 2014/0282546
Method for a Delayed Branch Implementation by Using a Front End Track Table
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Publication: US 2014/0281438
Multiport Memory Cell Having Improved Density Area
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Method for Dependency Broadcasting Through a Block Organized Source View Data Structure
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Method and Apparatus to Increase the Speed of the Load Access and Data Return Speed Path Using Early Lower Address Bits
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Microprocessor Accelerated Code Optimizer and Dependency Reordering Method
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Microprocessor Accelerated Code Optimizer
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Publication: US 2015/0039859
Accelerated Code Optimizer for a Multiengine Microprocessor
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Publication: US 2015/0186144
Fast Unaligned Memory Access
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Cache Replacement Policy
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Publication: US 2015/0286576
Methods and Systems for Tracking Addresses Stored in Non-Home Cache Locations
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Publication: US 2016/0110294
Systems and Methods for Invalidating Directory of Non-Home Locations Ways
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Publication: US 2016/0110293
SYSTEMS AND METHODS FOR MANAGING INTER-CPU INTERRUPTS BETWEEN MULTIPLE CPUs
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Virtual Load Store Queue Having a Dynamic Dispatch Window with a Distributed Structure
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Publication: US 2015/0134934
Method and System for Filtering the Stores to Prevent All Stores from Having to Snoop Check Against All Words of a Cache
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Publication: US 2015/0095591
Lock-Based and Synch-Based Method for Out of Order Loads in a Memory Consistency Model Using Shared Memory Resources
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Publication: US 2015/0095588
Method and System for Implementing Recovery from Speculative Forwarding Miss-Predictions/Errors Resulting from Load Store Reordering and Optimization
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Publication: US 2015/0095629
Instruction Definition to Implement Load Store Reordering and Optimization
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Publication: US 2015/0095615
Virtual Load Store Queue Having a Dynamic Dispatch Window with a Unified Structure
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Publication: US 2015/0095618
Semaphore Method and System with Out of Order Loads in a Memory Consistency Model That Constitutes Loads Reading from Memory in Order
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Publication: US 2015/0100734
Disambiguation-Free Out of Order Load Store Queue
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Publication: US 2015/0100765
Reordered Speculative Instruction Sequences with a Disambiguation-Free Out of Order Load Store Queue
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Publication: US 2015/0100766
Load Store Buffer Agnostic to Threads Implementing Forwarding from Different Threads Based on Store Seniority
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Publication: US 2015/0205605
Systems and Methods for Accessing a Unified Translation Lookaside Buffer
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Publication: US 2015/0301954
Method and Apparatus for Providing Hardware Support for Self-Modifying Code
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Publication: US 2015/0324213
Apparatus and Method for Processing an Instruction Matrix Specifying Parallel and Dependent Operations
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Using a Plurality of Conversion Tables to Implement an Instruction Set Agnostic Runtime Architecture
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An Allocation and Issue Stage for Reordering a Microinstruction Sequence into an Optimized Microinstruction Sequence to Implement an Instruction Set Agnostic Runtime Architecture
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Publication: US 2016/0026486
System for an Instruction Set Agnostic Runtime Architecture
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Application: 14/807,271 →
Publication: US 2016/0026483
System Converter That Implements a Reordering Process Through Jit (Just in Time) Optimization That Ensures Loads Do Not Dispatch Ahead of Other Loads That Are to the Same Address
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Application: 14/807,308 →
Publication: US 2016/0026444
Using a Conversion Look Aside Buffer to Implement an Instruction Set Agnostic Runtime Architecture
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Publication: US 2016/0026487
System Converter That Executes a Just in Time Optimizer for Executing Code from a Guest Image
Application: 14/807,343 →
Publication: US 2016/0026484
System Converter That Implements a Run Ahead Run Time Guest Instruction Conversion/Decoding Process and a Prefetching Process Where Guest Code Is Pre-Fetched from the Target of Guest Branches in an Instruction Sequence
Application: 14/807,353 →
Publication: US 2016/0026445
Systems and Methods for Faster Read After Write Forwarding Using a Virtual Address
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Application: 14/819,255 →
Publication: US 2015/0339238
Methods and Systems for Managing Synonyms in Virtually Indexed Physically Tagged Caches
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Publication: US 2016/0224471
Systems and Methods for Supporting a Plurality of Load and Store Accesses of a Cache
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Application: 14/922,035 →
Publication: US 2016/0041913
Systems and Methods for Maintaining the Coherency of a Store Coalescing Cache and a Load Cache
Patent: 9,720,831 →
Application: 14/922,042 →
Publication: US 2016/0041908
Systems and Methods for Supporting a Plurality of Load Accesses of a Cache in a Single Cycle
Application: 14/922,053 →
Publication: US 2016/0041930
Multilevel Conversion Table Cache for Translating Guest Instructions to Native Instructions
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Publication: US 2017/0161074
Systems and Methods for Non-Blocking Implementation of Cache Flush Instructions
Patent: 9,842,056 →
Application: 15/003,486 →
Publication: US 2016/0140044
Variable Caching Structure for Managing Physical Storage
Patent: 9,753,856 →
Application: 15/009,684 →
Publication: US 2016/0224472
Memory Fragments for Supporting Code Block Execution by Using Virtual Cores Instantiated by Partitionable Engines
Patent: 9,921,845 →
Application: 15/019,920 →
Publication: US 2016/0154653
Hardware Acceleration Components for Translating Guest Instructions to Native Instructions
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Publication: US 2017/0024212
Executing Instruction Sequence Code Blocks by Using Virtual Cores Instantiated by Partitionable Engines
Patent: 9,990,200 →
Application: 15/082,359 →
Publication: US 2016/0210145
Register File Segments for Supporting Code Block Execution by Using Virtual Cores Instantiated by Partitionable Engines
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Application: 15/082,867 →
Publication: US 2016/0210176
Systems and Methods for Implementing Weak Stream Software Data and Instruction Prefetching Using a Hardware Data Prefetcher
Application: 15/145,615 →
Publication: US 2016/0246727
Multiport Memory Cell Having Improved Density Area
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Publication: US 2016/0260475
Guest Instruction Block with Near Branching and Far Branching Sequence Construction to Native Instruction Block
Patent: 9,921,842 →
Application: 15/176,079 →
Publication: US 2016/0283239
Guest to Native Block Address Mappings and Management of Native Code Storage
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Publication: US 2016/0321077
Method and Apparatus for Sorting Elements in Hardware Structures
Patent: 9,753,734 →
Application: 15/215,004 →
Publication: US 2016/0328238
An Interconnect System to Support the Execution of Instruction Sequences by a Plurality of Partitionable Engines
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Publication: US 2016/0335130
Method and Apparatus to Avoid Deadlock During Instruction Scheduling Using Dynamic Port Remapping
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Publication: US 2016/0335091
Systems and Methods for Load Canceling in a Processor That Is Connected to an External Interconnect Fabric
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Methods, Systems and Apparatus for Predicting the Way of a Set Associative Cache
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Systems and Methods for Accessing a Unified Translation Lookaside Buffer
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Microprocessor Accelerated Code Optimizer
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Time-lag sliced architecture (TLSA)
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Ultra Large Instruction Block architecture (ULIB)
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Processor architectures and methods
Application: 60/792,219 →
Efficient Context Switch Architecture
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Self-Generating and Synchronizing Dynamic and Static Threading Architecture
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Unified Architecture for Dynamic Generation, Execution, Synchronization and Parallelization of Complex Instruction Formats
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Virtual Register File, Register Cache and Register File Hierarchy for Unified Parallel Architectures
Application: 60/865,820 →
Single Cycle Multi-Branch Prediction Including Shadow Cache for Early Far Branch Prediction
Application: 61/384,198 →
Instruction Sequence Buffer to Enhance Branch Prediction Efficiency
Application: 61/392,391 →
Instruction Sequence Buffer to Store Branches Having Reliably Predictable Instruction Sequences
Application: 61/392,392 →
Guest to Native Block Address Mappings and Management of Native Code Storage
Application: 61/436,957 →
Variable Caching Structure for Managing Physical Storage
Application: 61/436,959 →
Guest Instruction to Native Instruction Range Based Mapping Using a Conversion Look Aside Buffer of a Processor
Application: 61/436,962 →
Hardware Acceleration Components for Translating Guest Instructions to Native Instructions
Application: 61/436,966 →
Multilevel Conversion Table Cache for Translating Guest Instructions to Native Instructions
Application: 61/436,973 →
Guest Instruction Block with Near Branching and Far Branching Sequence Constrution to Native Instruction Block
Application: 61/436,975 →
Register File Segments for Supporting Code Block Execution by Using Virtual Cores Instantiated by Partitionable Engines
Application: 61/467,939 →
Memory Fragments for Supporting Code Block Execution by Using Virtual Cores Instantiated by Partitionable Engines
Application: 61/467,940 →
Executing Instruction Sequence Code Blocks by Using Virtual Cores Instantiated by Partitionable Engines
Application: 61/467,944 →
Decentrallized Allocation of Resources and Interconnnect Structures to Support the Execution of Instruction Sequences by a Plurality of Engines
Application: 61/488,662 →
Interconnect Structure to Support the Execution of Instruction Sequences by a Plurality of Engines
Application: 61/488,683 →
Lock-Based and Synch-Based Method for Out of Order Loads in a Memory Consistency Model Using Shared Memory Resources
Application: 61/660,521 →
Load Store Buffer Agnostic to Threads Implementing Forwarding from Different Threads Based on Store Seniority
Application: 61/660,526 →
Disambiguation-Free Out of Order Load Store Queue
Application: 61/660,528 →
Method and System for Implementing Recovery from Speculative Forwarding Miss-Predictions/Errors Resulting from Load Store Reordering and Optimization
Application: 61/660,538 →
Reordered Speculative Instruction Sequences with a Disambiguation-Free Out of Order Load Store Queue
Application: 61/660,539 →
Virtual Load Store Queue Having a Dynamic Dispatch Window with a Unified Structure
Application: 61/660,544 →
Virtual Load Store Queue Having a Dynamic Dispatch Window with a Distributed Structure
Application: 61/660,548 →
Method and System for Filtering the Stores to Prevent All Stores from Having to Snoop Check Against All Words of a Cache
Application: 61/660,553 →
Semaphore Method and System with Out of Order Loads in a Memory Consistency Model That Constitutes Loads Reading from Memory in Order
Application: 61/660,592 →
Instruction Definition to Implement Load Store Reordering and Optimization
Application: 61/660,610 →
Method and Apparatus to Allow Early Dependency Resolution and Data Forwarding in a Microprocessor
Application: 61/792,676 →
Method and Apparatus for Nearest Potential Store Tagging
Application: 61/792,885 →
Method and Apparatus for Preventing Non-Temporal Entries from Polluting Small Structures Using a Transient Buffer
Application: 61/793,042 →
Method and Apparatus for Guest Return Address Stack Emulation Supporting Speculation
Application: 61/793,174 →
Method and Apparatus for Predicting Forwarding of Data from a Store to a Load
Application: 61/793,466 →
Method and Apparatus to Avoid Deadlock During Instruction Scheduling Using Dynamic Port Remapping
Application: 61/793,541 →
Method and Apparatus for Predicting the Way of Set Associative Shadow Cache
Application: 61/793,703 →
Method and Apparatus for Sorting Elements in Hardware Structures
Application: 61/793,752 →
Method for Populating a Source View Data Structure by Using Register Template Snapshots
Application: 61/798,988 →
Method for Populating Register View Data Structure by Using Register Template Snapshots
Application: 61/799,006 →
Method and Apparatus for Efficient Scheduling for Asymmetrical Execution Units
Application: 61/799,062 →
Method and Apparatus to Speed Up the Load Access and Data Return Speed Path Using Early Calculated Lower Address Bits
Application: 61/799,116 →
Method for Populating and Instruction View Data Structure by Using Register Template Snapshots
Application: 61/799,299 →
Method for Dependency Broadcasting Through a Source Organized Source View Data Structure
Application: 61/799,407 →
Method for Dependency Broadcasting Through a Block Organized Source View Data Structure
Application: 61/799,530 →
Method and Apparatus for a Wide and Efficient Front-End to Emulate a Guest-Architecture
Application: 61/799,717 →
Method for Implementing a Reduced Size Register View Data Structure in a Microprocessor
Application: 61/799,736 →
Method for Implementing a Reduced Size Register View Data Structure in a Microprocessor
Application: 61/799,892 →
Method for Executing Blocks of Instructions Using a Microprocessor Architecture Having a Register View, Source View, Instruction View, and a Plurality of Register Templates
Application: 61/799,902 →
Method for Executing Multithreaded Instructions Grouped into Blocks
Application: 61/800,123 →
Method for Performing Dual Dispatch of Blocks and Half Blocks
Application: 61/800,179 →
Method for Emulating a Guest Centralized Flag Architecture by Using a Native Stupid Flag Architecture
Application: 61/800,487 →
Systems and Methods for Supporting a Plurality of Load Accesses of a Cache in a Single Cycle to Maintain Throughput
Application: 61/800,498 →
Multiport Memory Cell Having Improved Density Area
Application: 61/800,885 →
Method for a delayed branch implementation by using a front end track table
Application: 61/852,057 →
Method for a staged optimized high-speed adder
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Method and Apparatus for Providing Hardware Support for Self-Modifying Code
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Runtime Architecture for Efficiently Optimizing and Executing Guest Code and Converting to Native Code
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Related Assignments (9)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Oct 24, 2016
From: ABDALLAH, MOHAMMAD
To: SOFT MACHINES, INC.
Reel/Frame 040261/0724 →
Assignment of Assignor's Interest Oct 24, 2016
From: A, MOHAMMAD
To: SOFT MACHINES, INC.
Reel/Frame 040261/0989 →
Assignment of Assignor's Interest Oct 24, 2016
From: ABDALLAH, MOHAMMAD
To: SOFT MACHINES, INC.
Reel/Frame 040266/0842 →
Assignment of Assignor's Interest Oct 24, 2016
From: ABDALLAH, MOHAMMAD
To: SOFT MACHINES, INC.
Reel/Frame 040266/0860 →
Assignment of Assignor's Interest Oct 24, 2016
From: ABDALLAH, MOHAMMAD
To: SOFT MACHINES, INC.
Reel/Frame 040266/0877 →
Assignment of Assignor's Interest Oct 24, 2016
From: ABDALLAH, MOHAMMAD
To: SOFT MACHINES, INC.
Reel/Frame 040266/0894 →
Assignment of Assignor's Interest Oct 24, 2016
From: ABDALLAH, MOHAMMAD
To: SOFT MACHINES, INC.
Reel/Frame 040268/0338 →
Confirmatory Patent Assignment Oct 27, 2016
From: ABDALLAH, MOHAMMAD
To: SOFT MACHINES, INC.
Reel/Frame 040503/0610 →
Corrective Assignment to Correct the Assignor Name Previously Recorded at Reel: 040261 Frame: 0989. Assignor(S) Hereby Confirms the Assignment. Jan 17, 2017
From: ABDALLAH, MOHAMMAD
To: SOFT MACHINES, INC.
Reel/Frame 041127/0163 →