Systems and methods for managing inter-CPU interrupts between multiple CPUs
View Patent ↗Methods for managing inter-CPU interrupts between sending and receiving CPUs are disclosed. As a part of a method, a target CPU identifier and an interrupt number is written in an interrupt send register of an interrupt sending CPU, the interrupt number is written into one of a plurality of locations of an interrupt receive register corresponding to the target CPU, an identifier of the location of the highest priority interrupt of a plurality of interrupts received by the interrupt receive register is written in an interrupt pick register, the interrupt pick register is read to determine the highest priority interrupt and a matrix associated with the target CPU is read to determine the sender of the highest priority interrupt. The highest priority interrupt is processed.
1. A method for managing inter-CPU interrupts, comprising:
writing a target CPU interrupt number in an interrupt send register of an interrupt sending CPU;
writing said interrupt number in one of a plurality of locations of an interrupt receive register corresponding to said target CPU, wherein said interrupt number is received from said interrupt send register;
writing an identifier of a location of a highest priority interrupt number of a plurality of interrupts received in said interrupt receive register in an interrupt pick register;
reading said interrupt pick register to determine the highest priority interrupt number;
reading a matrix associated with said target CPU to determine the sender of the highest priority interrupt number; and
processing an interrupt associated with said highest priority interrupt number after identifying the sender of the highest priority interrupt number.
2. The method of claim 1 wherein said sending CPU can send an interrupt to a plurality of CPUs via said interrupt send register.
3. The method of claim 1 wherein when writing said interrupt number in one of a plurality of locations of an interrupt receive register a bit in said interrupt receive register is set which corresponds to a received interrupt number.
4. The method of claim 3 wherein if said bit in said interrupt receive register is changed from 0 to 1 an exception is raised.
5. The method of claim 1 wherein an interrupt can be acknowledged by writing a 0 to an interrupt number bit.
6. The method of claim 1 wherein a read of said interrupt pick register elicits the highest priority interrupt number with a valid bit set to 1.
7. The method of claim 1 wherein a read of said interrupt pick register causes a resetting of the bit in the receive register of the interrupt number that is read.
8. The method of claim 1 wherein said matrix is a pointer to a memory location in which an interrupt packet from a sender is stored.
9. A CPU operable to manage inter-CPU interrupts comprising:
a processing component;
a register managing component for managing a plurality of registers, comprising:
an interrupt send register for sending a target CPU interrupt number;
an interrupt receive register for receiving interrupt numbers that are stored in one of a plurality of locations of said receive register, wherein said interrupt numbers are received from said interrupt send register; and
an interrupt pick register for storing a highest priority interrupt number of said interrupt numbers that are received by said interrupt receive register;
and,
a matrix reading component for reading a matrix associated with another CPU to determine a sender of a highest priority interrupt associated with said highest priority interrupt number.
10. The CPU of claim 9 wherein said interrupt send register can send an interrupt to a plurality of CPUs via said interrupt send register.
11. The CPU of claim 9 wherein said interrupt receive register has a bit which when set indicates a received interrupt number.
12. The CPU of claim 11 wherein if said bit in said interrupt receive register is changed from 0 to 1 an exception is raised.
13. The CPU of claim 9 wherein an interrupt can be acknowledged by writing a 0 to an interrupt number bit.
14. The CPU of claim 9 wherein said interrupt pick register provides the highest priority interrupt number with a valid bit set to 1.
15. The CPU of claim 9 wherein said interrupt pick register causes a resetting of a bit in the interrupt receive register of an interrupt number that is read.
16. A processor comprising a plurality of CPUs with each CPU comprising:
a processing component;
a register managing component for managing a plurality of registers, comprising:
an interrupt send register for sending a target CPU interrupt number;
an interrupt receive register for receiving interrupt numbers that are stored in one of a plurality of locations of said receive register, wherein said interrupt numbers are received from said interrupt send register; and
an interrupt pick register for storing a highest priority interrupt number of said interrupt numbers that are received by said interrupt receive register;
and,
a matrix reading component for reading a matrix associated with another CPU to determine a sender of a highest priority interrupt associated with said highest priority interrupt number.
17. The processor of claim 16 wherein said interrupt send register can send an interrupt to a plurality of CPUs via said interrupt send register.
18. The processor of claim 17 wherein said interrupt receive register has a bit which when set indicates a received interrupt number.
19. The processor of claim 16 wherein if said bit in said interrupt receive register is changed from 0 to 1 an exception is raised.
20. The processor of claim 16 wherein an interrupt can be acknowledged by writing a 0 to an interrupt number bit.