Variable caching structure for managing physical storage

1. A method for managing a variable caching structure for managing storage for a processor, comprising:

receiving a request for a guest address;

accessing a multi-way tag array to determine whether there exists a pointer in the multi-way tag array that corresponds to the guest address;

upon a hit on a tag of the multi-way tag array, accessing a corresponding entry to retrieve the pointer, wherein the pointer corresponds to a location in a storage stack where a corresponding group of storage blocks of converted native instructions is stored; and

accessing the converted native instructions from the storage stack for execution.

2. The method of claim 1 further comprising:

using the multi-way tag array to store a plurality of pointers for a corresponding plurality of different size groups of physical storage of the storage stack, wherein the plurality of pointers indicate guest addresses that have corresponding converted native addresses stored within the storage stack;

allocating a group of storage blocks of the storage stack, wherein a size of an allocation is in accordance with a corresponding size of one of the plurality of different size groups;

storing a plurality of blocks of converted native instructions onto the storage stack in accordance with the allocating of group of storage blocks.

3. The method of claim 2 , wherein the different size groups of physical storage of a storage stack implements a precise allocation of storage in accordance with variable size traces of instructions.

4. The method of claim 1 , wherein tags of the multi-way tag array can comprise two or more sub-tags.

5. The method of claim 1 , wherein entries of the multi-way tag array are invalidated by overwriting their respective tags to recover allocated space on the storage stack.

6. The method of claim 1 , wherein an extended way tag structure is used to store a plurality of extended ways to enable the processor to extend locality of reference in a different way from the multi-way tag array.

7. The method of claim 6 , wherein the extended way tag structure implements storage of additional ways for matching a trace of instructions that have become frequently encountered.

8. The method of claim 6 , wherein entries of the multi-way tag array includes an extended way bit, wherein the extended way bit indicates whether additional ways for the entries reside within the extended way tag structure.

9. A system for managing a variable caching structure for managing storage for a processor, comprising:

a multi-way tag array for storing a plurality of pointers for a corresponding plurality of different size groups of physical storage, wherein the plurality of pointers indicate guest addresses that have corresponding converted native addresses stored within the physical storage;

wherein upon receiving a request for a guest address, the multi-way tag array is accessed to determine whether there exists a pointer in the multi-way tag array that corresponds to the guest address;

wherein upon a hit on a tag of the multi-way tag array, a corresponding entry is accessed to retrieve the pointer, wherein the pointer indicates a location in the physical storage having native instructions, and the native instructions are accessed from the physical storage for execution.

10. The system of claim 9 , wherein physical storage comprises a storage stack, wherein a group of storage blocks of the storage stack are allocated, wherein a size of an allocation is in accordance with a corresponding size of one of the plurality of different size groups, and wherein a plurality of blocks of native instructions are stored onto the storage stack in accordance with the allocating of group of storage blocks.

11. The system of claim 9 , wherein the different size groups of physical storage of a storage stack implements a precise allocation of storage in accordance with variable size traces of instructions.

12. The system of claim 9 , wherein tags of the multi-way tag array can comprise two or more sub-tags.

13. The system of claim 10 , wherein entries of the multi-way tag array are invalidated by overwriting their respective tags to recover allocated space on the storage stack.

14. The system of claim 9 , wherein an extended way tag structure is used to store a plurality of extended ways to enable the processor to extend locality of reference in a different way from the multi-way tag array.

15. The system of claim 14 , wherein the extended way tag structure implements storage of additional ways for matching a trace of instructions that have become frequently encountered.

16. The system of claim 14 , wherein entries of the multi-way tag array includes an extended way bit, wherein the extended way bit indicates whether additional ways for the entries reside within the extended way tag structure.

17. A microprocessor that implements a method for managing a variable caching structure for managing storage for a processor, the microprocessor comprising:

a multi-way tag array for storing a plurality of pointers for a corresponding plurality of different size groups of physical storage, wherein the plurality of pointers indicate guest addresses that have corresponding converted native addresses stored within the physical storage;

wherein upon receiving a request for a guest address, the multi-way tag array is accessed to determine whether there exists a pointer in the multi-way tag array that corresponds to the guest address;

wherein upon a hit on a tag of the multi-way tag array, a corresponding entry is accessed to retrieve the pointer, wherein the pointer indicates a location in the physical storage having native instructions, and the native instructions are accessed from the physical storage for execution.

18. The microprocessor of claim 17 , wherein physical storage comprises a storage stack, wherein a group of storage blocks of the storage stack are allocated, wherein a size of an allocation is in accordance with a corresponding size of one of the plurality of different size groups, and wherein a plurality of blocks of native instructions are stored onto the storage stack in accordance with the allocating of group of storage blocks.

19. The microprocessor of claim 17 , wherein the different size groups of physical storage of a storage stack implements a precise allocation of storage in accordance with variable size traces of instructions.

20. The microprocessor of claim 17 , wherein entries of the multi-way tag array are invalidated by overwriting their respective tags to recover allocated space on the storage stack.