Apparatus and method for processing an instruction matrix specifying parallel and dependent operations
View Patent ↗A matrix of execution blocks form a set of rows and columns. The rows support parallel execution of instructions and the columns support execution of dependent instructions. The matrix of execution blocks process a single block of instructions specifying parallel and dependent instructions.
1. A processor, comprising:
execution units;
a register file with multiple register segments to store results for subsequent processing by the execution units, wherein the register file is configurable for different execution modes, including:
the multiple register segments forming a single register file where each register segment stores sources and results of a Multiple Instructions Multiple Data (MIMD) super instruction issuing simultaneous instructions where each individual instruction is a scalar or Single Instruction Multiple Data (SIMD);
the multiple register segments forming individual independent register files with individual register state to support simultaneous processing of separate threads, wherein each instruction is associated with a separate thread and a separate register file segment; and
the multiple register segments forming a single thread register file, wherein register segments are duplicated in multiple segments of the register file to store results of simultaneously executed non-dependent instructions that are dynamically issued from a single thread instruction sequence.
2. The processor of claim 1 wherein the instructions are issued by a run time system.
3. The processor of claim 1 wherein the instructions are issued by hardware.
4. The processor of claim 1 wherein the instructions are issued by a compiler.
5. The processor of claim 1 configured to access multiple register segments of duplicate register files.
6. The processor of claim 1 configured to store instruction execution results in different register segments of duplicate register files.
7. The processor of claim 1 configured to designate registers for instruction results and source operands.
8. The processor of claim 1 configured to read instruction operands using listed sources and destinations in fixed locations regardless of opcode.
9. The processor of claim 8 configured to determine dependency between instructions based upon the listed sources and destinations regardless of opcode.
10. The processor of claim 1 wherein the execution units support floating point, integer, Single Instruction Multiple Data (SIMD), and Multiple Instruction Multiple Data (MIMD) operations.
11. The processor of claim 1 wherein the register file has a hierarchy that supports parallel block writes without an increase in a number of ports.
12. The processor of claim 1 wherein subsets of execution units form execution blocks, each configured to perform a common set of operations.
13. The processor of claim 12 wherein each execution block has the same processing latency.
14. The processor of claim 12 wherein each execution block is a symmetric instantiation to a scheduler.