Method and apparatus for preventing non-temporal entries from polluting small structures using a transient buffer

1. A method for preventing non-temporal entries from entering small critical structures, said method comprising:

transferring a first entry from a higher level memory structure to an intermediate buffer;

determining a second entry to be evicted from said intermediate buffer and a corresponding value associated with said second entry, wherein the intermediate buffer is a temporary buffer in between the higher level memory structure and a lower level memory structure and operable to temporarily store entries from the higher level memory structure;

responsive to a determination that said second entry is frequently accessed, installing said second entry from said intermediate buffer into the lower level memory structure, wherein the intermediate buffer lies in an intermediate position between the higher level memory structure and the lower level memory structure, and wherein said lower level structure is a conversion lookaside buffer, and wherein each entry in said conversion lookaside buffer is a mapping between a guest address and a corresponding native address; and

installing said first entry into a slot previously occupied by said second entry in said intermediate buffer.

2. The method of claim 1 , wherein said higher level memory structure comprises a Level 2 cache memory.

3. The method of claim 1 , wherein said lower level memory structure is chosen from a group consisting of: a L1 data cache memory, a L1 instruction cache memory and a conversion lookaside buffer.

4. The method of claim 1 , further comprising:

responsive to a determination that said second entry is not frequently accessed, discarding said second entry.

5. The method of claim 1 , wherein said determining is based on a replacement policy, wherein said replacement policy is selected from a group consisting of: an access counter based replacement policy, a least-recently used replacement policy and a random replacement policy.

6. The method of claim 1 , wherein said determination that said second entry is frequently accessed comprises computing that said count for said second entry is equal to or greater than a predetermined threshold value, and wherein said value associated with said second entry is a counter value.

7. A processor unit configured to perform a method for preventing non-temporal entries from entering small critical structures, said method comprising:

transferring a first entry from a higher level memory structure to an intermediate buffer;

determining a second entry to be evicted from said intermediate buffer and a corresponding value associated with said second entry, wherein the intermediate buffer is a temporary buffer in between the higher level memory structure and a lower level memory structure and operable to temporarily store entries from the higher level memory structure;

responsive to a determination that said second entry is frequently accessed, installing said second entry from said intermediate buffer into the lower level memory structure, wherein the intermediate buffer lies in an intermediate position between the higher level memory structure and the lower level memory structure, and wherein said lower level structure is a conversion lookaside buffer, and wherein each entry in said conversion lookaside buffer is a mapping between a guest address and a corresponding native address; and

installing said first entry into a slot previously occupied by said second entry in said intermediate buffer.

8. The method of claim 7 , wherein said higher level memory structure comprises a Level 2 cache memory.

9. The method of claim 7 , wherein said lower level memory structure is chosen from a group consisting of: a L1 data cache memory, a L1 instruction cache memory and a conversion lookaside buffer.

10. The method of claim 7 , further comprising:

responsive to a determination that said second entry is not frequently accessed, discarding said second entry.

11. The method of claim 7 , wherein said determining is based on a replacement policy, wherein said replacement policy is selected from a group consisting of: an access counter based replacement policy, a least-recently used replacement policy and a random replacement policy.

12. The method of claim 7 , wherein said determination that said second entry is frequently accessed comprises computing that said count for said second entry is equal to or greater than a predetermined threshold value, and wherein said value associated with said second entry is a counter value.

13. An apparatus for preventing non-temporal entries from entering small critical structures, said apparatus comprising:

a memory;

a processor communicatively coupled to said memory, wherein said processor is configured to:

transfer a first entry from a higher level memory structure to an intermediate buffer, wherein the intermediate buffer is a temporary buffer in between the higher level memory structure and a lower level memory structure and operable to temporarily store entries from the higher level memory structure;

determine a second entry to be evicted from said intermediate buffer and a corresponding value associated with said second entry;

responsive to a determination that said second entry is frequently accessed, install said second entry from said intermediate buffer into the lower level memory structure, wherein the intermediate buffer lies in an intermediate position between the higher level memory structure and the lower level memory structure, and wherein said lower level structure is a conversion lookaside buffer, and wherein each entry in said conversion lookaside buffer is a mapping between a guest address and a corresponding native address; and

install said first entry into a slot previously occupied by said second entry in said intermediate buffer.

14. The apparatus of claim 13 , wherein said higher level memory structure comprises a Level 2 cache memory.

15. The apparatus of claim 13 , wherein said lower level memory structure is chosen from a group consisting of: a L1 data cache memory, a L1 instruction cache memory and a conversion lookaside buffer.

16. The apparatus of claim 13 , wherein said processor is further configured to discard said second entry responsive to a determination that said second entry is not frequently accessed.

17. The apparatus of claim 13 , wherein said processor is configured to determine said second entry to be evicted based on a replacement policy, wherein said replacement policy is selected from a group consisting of: an access counter based replacement policy, a least-recently used replacement policy and a random replacement policy.