Systems and methods for read request bypassing a last level cache that interfaces with an external fabric
Methods for read request bypassing a last level cache which interfaces with an external fabric are disclosed. A method includes identifying a read request for a read transaction, generating a phantom read transaction identifier for the read transaction and forwarding the read transaction with the phantom read transaction identifier beyond a last level cache before detection of a hit or miss with respect to the read transaction. The phantom read transaction identifier acts as a pointer to a real read transaction identifier.
1. A method for read request bypassing a last level cache which interfaces with an external fabric, the method comprising:
accessing a read request for a read transaction;
generating a phantom read transaction identifier for said read transaction; and
forwarding said read transaction with said phantom read transaction identifier beyond a last level cache before detection of a hit or a miss with respect to said read transaction, wherein said read transaction that is forwarded beyond said last level cache is canceled if said read transaction is a hit in said last level cache or does not access said last level cache, and wherein said phantom read transaction identifier is converted to a pointer to a real read transaction identifier if said read transaction is a miss in said last level cache.
2. The method of claim 1 wherein said phantom read transaction identifier comprises a bit set to differentiate said phantom read transaction identifier from said real read transaction identifier.
3. The method of claim 1 wherein for a 32 entry load queue said phantom read transaction identifier is associated with one bit of six bits.
4. The method of claim 1 further comprising supplying said phantom read transaction identifier from said last level cache.
5. The method of claim 1 wherein said real read transaction identifier is a pointer to a read queue in said last level cache.
6. A cache controller, comprising:
an accessor for accessing a read request for a read transaction;
a generator for generating a phantom read transaction identifier for said read transaction; and
a forwarder for forwarding said read transaction with said phantom read transaction identifier beyond a last level cache before detection of a hit or a miss with respect to said read transaction, wherein said read transaction that is forwarded beyond said last level cache is canceled if said read transaction is a hit in said last level cache or does not access said last level cache, and wherein said phantom read transaction identifier is converted to a pointer to a real read transaction identifier if said read transaction is a miss in said last level cache.
7. The cache controller of claim 6 wherein said phantom read transaction identifier comprises a bit set to differentiate said phantom read transaction identifier from said real read transaction identifier.
8. The cache controller of claim 6 wherein for a 32 entry load queue said phantom read transaction identifier is associated with one bit of six bits.
9. The cache controller of claim 6 wherein said phantom read transaction identifier is supplied from said last level cache.
10. The cache controller of claim 6 wherein said real read transaction identifier is a pointer to a read queue in said last level cache.
11. A processor, comprising:
a CPU;
a cache system; and
a cache controller, wherein said cache controller comprises:
an accessor for accessing a read request for a read transaction;
a generator for generating a phantom read transaction identifier for said read transaction; and
a forwarder for forwarding said read transaction with said phantom read transaction identifier beyond a last level cache before detection of a hit or a miss with respect to said read transaction, wherein said read transaction that is forwarded beyond said last level cache is canceled if said read transaction is a hit in said last level cache or does not access said last level cache, and wherein said phantom read transaction identifier is converted to a pointer to a real read transaction identifier if said read transaction is a miss in said last level cache.
12. The processor of claim 11 wherein said phantom read transaction identifier comprises a bit set to differentiate said phantom read transaction identifier from said real read transaction identifier.
13. The processor of claim 11 wherein for a 32 entry load queue said phantom read transaction identifier is associated with one bit of six bits.
14. The processor of claim 11 wherein said phantom read transaction identifier is supplied from said last level cache.
15. The method of claim 1 wherein said generating said phantom read transaction identifier is performed by a cache controller.