Methods, systems and apparatus for predicting the way of a set associative cache
View Patent ↗A method for predicting a way of a set associative shadow cache is disclosed. As a part of a method, a request to fetch a first far taken branch instruction of a first cache line from an instruction cache is received, and responsive to a hit in the instruction cache, a predicted way is selected from a way array using a way that corresponds to the hit in the instruction cache. A second cache line is selected from a shadow cache using the predicted way and the first cache line and the second cache line are forwarded in the same clock cycle.
1. A method for predicting a way of a set associative shadow cache, comprising:
receiving a request to fetch a first far taken branch instruction of a first cache line from an instruction cache;
responsive to a hit in said instruction cache, selecting a predicted way from a way array using a way that corresponds to said hit; and
selecting a second cache line that is stored at the target of said first far taken branch instruction from a shadow cache using said predicted way and forwarding said first cache line and said second cache line in the same clock cycle.
2. The method of claim 1 further comprising:
in response to said receiving a request, reading a plurality of components of an L1 cache.
3. The method of claim 1 wherein a determination of said hit is based on an instruction cache tag.
4. The method of claim 1 wherein said predicted way comprises a predetermined number of bits.
5. The method of claim 1 wherein said predicted way is stored in said array per way of said instruction cache.
6. The method of claim 1 further comprising:
comparing said predicted way with a way indicated by a shadow cache tag storage component.
7. The method of claim 6 wherein said comparing is used to update said predicted way if said predicted way is incorrect.
8. A processor, comprising:
a CPU; and
a cache system, comprising:
a cache controller, wherein said cache controller comprises:
a request receiver for receiving a request to fetch a first far taken branch instruction of a first cache line from an instruction cache;
a predicted way selector for, responsive to a hit in said instruction cache, selecting a predicted way from a way array using a way that corresponds to said hit; and
a data selector for selecting a second cache line that is stored at the target of the first far taken branch instruction from a shadow cache using said predicted way and forwarding said first cache line and said second cache line in the same clock cycle.
9. The processor of claim 8 further comprising:
a reader for, in response to said receiving a request, reading a plurality of components of an instruction cache.
10. The processor of claim 8 wherein a determination of said hit is based on an instruction cache tag.
11. The processor of claim 8 wherein said predicted way comprises a predetermined number of bits.
12. The processor of claim 8 wherein said predicted way is stored in said array per way of said instruction cache.
13. The processor of claim 8 further comprising:
a comparer for comparing said predicted way with a way indicated by a shadow cache tag storage component.
14. The processor of claim 13 wherein said comparing is used to update said predicted way if said predicted way is incorrect.
15. A cache controller, comprising:
a request receiver for receiving a request to fetch a first far taken branch instruction of a first cache line from an instruction cache;
a predicted way selector for, responsive to a hit in said instruction cache, selecting a predicted way from a way array using a way that corresponds to said hit; and
a data selector for selecting a second cache line that is stored at the target of the first far taken branch instruction from a shadow cache using said predicted way and forwarding said first cache line and said second cache line in the same clock cycle.
16. The cache controller of claim 15 further comprising:
a reader for, in response to said receiving a request, reading a plurality of components of an instruction cache.
17. The cache controller of claim 15 wherein a determination of said hit is based on an instruction cache tag.
18. The cache controller of claim 15 wherein said predicted way comprises a predetermined number of bits.
19. The cache controller of claim 15 wherein said predicted way is stored in said array per way of said instruction cache.
20. The cache controller of claim 15 further comprising:
a comparer for comparing said predicted way with a way indicated by a shadow cache tag storage component.