Methods, systems and apparatus for predicting the way of a set associative cache
View Patent ↗A method for predicting a way of a set associative shadow cache is disclosed. As a part of a method, a request to fetch a first far taken branch instruction of a first cache line from an instruction cache is received, and responsive to a hit in the instruction cache, a predicted way is selected from a way array using a way that corresponds to the hit in the instruction cache. A second cache line is selected from a shadow cache using the predicted way and the first cache line and the second cache line are forwarded in the same clock cycle.
1. A method of predicting a way of a set associative shadow cache, the method comprising:
receiving a request to fetch a first far taken branch instruction of a first cache line from an instruction cache;
responsive to a hit in said instruction cache, selecting a predicted way from a way array; and
selecting a second cache line that is stored at a target of said first far taken branch instruction from a shadow cache using said predicted way.
2. The method of claim 1 , further comprising:
forwarding said first cache line and said second cache line in the same clock cycle.
3. The method of claim 2 , further comprising:
forwarding said first cache line and said second cache line to a processor scheduler and execution units.
4. The method of claim 1 , further comprising:
predicting a target of said first far taken branch, wherein said target is in a different cache-line; and
copying said second cache line that is stored at the target of said first far taken branch instruction into said shadow cache.
5. The method of claim 1 , further comprising:
using a way of said instruction cache where said hit occurs to perform said selecting.
6. The method of claim 1 further comprising:
in response to said receiving a request, reading a plurality of components of an L1 cache.
7. The method of claim 1 , wherein a determination of said hit is based on an instruction cache tag.
8. The method of claim 1 , wherein said predicted way comprises a predetermined number of bits.
9. The method of claim 1 further comprising:
comparing said predicted way with a way indicated by a shadow cache tag storage component.
10. The method of claim 9 wherein said comparing is used to update said predicted way if said predicted way is incorrect.
11. A method of predicting a way of a set associative shadow cache, the method comprising:
receiving a request to fetch a first far taken branch instruction of a first cache line from an instruction cache;
responsive to a hit in said instruction cache, selecting a target of said first far taken branch instruction stored in an information cache using a way that corresponds to said hit; and
selecting a second cache line that is stored at said target of said first far taken branch instruction from a shadow cache using said target address.
12. The method of claim 11 , further comprising:
forwarding said first cache line and said second cache line in the same clock cycle.
13. The method of claim 12 , further comprising:
forwarding said first cache line and said second cache line to a processor scheduler and execution units.
14. The method of claim 11 , wherein said selecting further comprises:
comparing said target of said first far taken branch instruction to tags in a shadow cache tag store to determine a way in said shadow cache that contains said second cache line.
15. A cache controller comprising:
a request receiver for receiving a request to fetch a first far taken branch instruction of a first cache line from an instruction cache;
a predicted way selector for, responsive to a hit in said instruction cache, selecting a predicted way from a way array using a way that corresponds to said hit; and
a data selector for selecting a second cache line that is stored at the target of the first far taken branch instruction from a shadow cache using said predicted way.
16. The cache controller of claim 15 , wherein said data selector forwards said first cache line and said second cache line in the same clock cycle.
17. The cache controller of claim 15 further comprising:
a reader for responsive to said receiving a request for reading a plurality of components of an instruction cache.
18. The cache controller of claim 15 wherein a determination of said hit is based on an instruction cache tag.
19. The cache controller of claim 15 wherein said predicted way comprises a predetermined number of bits.
20. The cache controller of claim 15 further comprising:
a comparer for comparing said predicted way with a way indicated by a shadow cache tag storage component.