Multiport memory cell having improved density area

1. A memory cell, comprising:

a data storing component;

a first memory access component coupled to a first side of said data storing component;

a second memory access component coupled to a second side of said data storing component;

a plurality of lines coupled to said first memory access component and said second memory access component; and

a read/write assist transistor, coupled to load transistors of said data storing component, wherein the read/write assist transistor during read operations is activated by a controller for the duration of the read operation and during write operations is activated by said controller to impress the desired voltage level before or after one or more memory access components activated as a part of the write operation are deactivated.

2. The memory cell of claim 1 , wherein said plurality of lines comprise:

first and second bit lines coupled to said first memory access component;

first and second bit lines coupled to said second memory access component;

first and second write lines coupled to said first memory access component; and

first and second write lines coupled to said second memory access component.

3. The memory cell of claim 2 , wherein said memory cell facilitates a differential write wherein either said first and second write lines coupled to said first memory access component or said first and second write lines coupled to said second memory access component are activated.

4. The memory cell of claim 2 , wherein said memory cell facilitates a single ended write operation wherein a single write line and a single transistor of one of said first memory access component and said second memory access component is activated.

5. The memory cell of claim 1 wherein said memory cell comprises cross-coupled inverters.

6. The memory cell of claim 1 wherein said read/write assist transistor is coupled to terminals of load transistors of said memory cell.

7. The memory cell of claim 1 wherein said read/write assist transistor is located inside said memory cell.

8. The memory cell of claim 1 wherein said memory access components are coupled to respective internal nodes of said memory cell.

9. The memory cell of claim 1 wherein said memory cell comprises nodes that provide true and complement voltage levels.

10. A processor, comprising:

a CPU;

registers coupled to said CPU;

cache memory components coupled to said CPU wherein said registers and/or said cache memory components include memory cells, and wherein a memory cell comprises:

a data storing component;

a first memory access component coupled to a first side of said data storing component;

a second memory access component coupled to a second side of said data storing component;

a plurality of lines coupled to said first memory access component and said second memory access component; and

a read/write assist transistor, coupled to load transistors of said data storing component, wherein the read/write assist transistor during read operations is activated by a CPU for the duration of the read operation and during write operations is activated by said CPU to impress the desired voltage level before or after one or more memory access components activated as a part of the write operation are deactivated.

11. The processor of claim 10 , wherein said plurality of lines of said memory cell comprises:

first and second bit lines coupled to said first memory access component;

first and second bit lines coupled to said second memory access component;

first and second write lines coupled to said first memory access component; and

first and second write lines coupled to said second memory access component.

12. The processor of claim 11 wherein said memory cell facilitates a differential write wherein either said first and second write lines coupled to said first memory access component of said first and second write lines coupled to said second memory access component are activated.

13. The processor of claim 11 wherein said memory cell facilitates a single

ended write operation wherein a single write line and a single transistor of one of said first memory access component and said second memory access component is activated.

14. The processor of claim 10 wherein said memory cell comprises cross-coupled inverters.

15. The processor of claim 10 wherein said read/write assist transistor is coupled to terminals of load transistors of said memory cell.

16. The memory cell of claim 10 wherein said read/write assist transistor is located inside said memory cell.

17. The processor of claim 10 wherein said memory access components are coupled to respective internal nodes of said memory cell.

18. The processor of claim 10 wherein said memory cell comprises nodes that provide true and complement voltage levels.

19. A method for accessing a memory cell, comprising:

in a mode comprising a read operation:

biasing one or more bit lines to a high voltage state;

turning a read/write assist component on;

placing a high voltage level onto the gate of a memory access component; and

determining if said memory access component is conducting, wherein said read/write assist transistor remains on for the duration of said read operation; and

in a mode comprising write operation:

biasing one or more bit lines to either a high or low voltage state;

placing a high voltage level onto the gate of a memory access component;

turning a read/write assist transistor on to impress the desired voltage level before or after said memory access component is turned off.

20. The method of claim 19 comprising executing a differential write wherein either first and second write lines coupled to a first memory access component or first and second write lines coupled to a second memory access component are activated.

21. The method of claim 19 comprising executing a single ended write operation wherein a single write line and a single transistor of one of a first memory access component and a second memory access component is activated.

22. The method of claim 19 wherein true and complement voltage levels

are provided.

23. A method for accessing a memory cell, comprising:

in a mode comprising a read operation:

biasing one or more bit lines to a high voltage state;

turning a read/write assist component on;

placing a high voltage level onto the gate of a memory access component; and

determining if said memory access component is conducting, wherein said read/write assist transistor remains on for the duration of said read operation.