Patent Assignment
Reel/Frame 061175/0176
Assignment of Assignor's Interest
Recorded: 2022-08-15
Pages: 220
Assignor
INTEL CORPORATION
Executed: 2022-07-18
Assignee
TAHOE RESEARCH, LTD.
BLANCHARDSTOWN CORPORATE PARK 2, PLAZA 255, SUITE 2A, DUBLIN, D15 YH6H, IRELAND
Covered Properties
(2765)
Method and System for Data Management in a Video Decoder
Patent:
6,823,016 →
Application:
09/027,014 →
System and Method for Creating and Displaying Classes of Graphical Display Objects
Patent:
7,941,756 →
Application:
09/576,359 →
Electronic programming guide with selectable categories
Application:
09/599,242 →
Digital Still Camera System and Method
Alert Management Messaging
Method and Apparatus to Manage Packet Fragmentation
Method and Apparatus for Adaptive Synchronization of Network Devices
Low Power Subsystem for Portable Computers
Patent:
7,725,748 →
Application:
09/753,326 →
Displaying Software Keyboard Images
Management of Links to Data Embedded in Blocks of Data
Method and Apparatus for Automatic Photograph Annotation
Mechanism for Handling Explicit Writeback in a Cache Coherent Multi-Node Architecture
Method and Apparatus for Combining Broadcast Schedules and Content on a Digital Broadcast-Enabled Client Platform
Smm Loader and Execution Mechanism for Component Software for Multiple Architectures
Fault Resilient Booting for Multiprocessor System Using Appliance Server Management
Method and System for Using Internal Fifo Ram to Improve System Boot Times
Correction of "Red-Eye" Effects in Images
Routing Messages Using Presence Information
Powering Down a Computer in Response to a Thermal Event
Apparatus and Method for Scalable Server Load Balancing
Navigation for Mpeg Streams
Voltage Regulation for Computer System Components That Increases Voltage Level When a Component Enters a Sleep State as Indicated by a Power State Status Signal
Compensating Organic Light Emitting Device Displays for Color Variations
Hash-Based Data Frame Distribution for Web Switches
Techniques for Storing and Retrieving Security Information Corresponding to Cryptographic Operations to Support Cryptographic Processing for Multiple Network Traffic Streams
Load Balancing and Fault Tolerance for Server-Based Software Applications
Camera Driven Virtual Workspace Management
Mechanism for Preventing Unnecessary Timeouts and Retries for Service Requests in a Cluster
Security Association Management Through the Use of Lookup Tables
Method and Apparatus for Performing Modular Multiplication
Operating Time Division Duplex (Tdd) Wireless Systems in Paired Spectrum (Fdd) Allocations
Patent:
7,336,626 →
Application:
09/967,637 →
System and Method to Implement a Cost-Effective Remote System Management Mechanism Using a Serial Communication Controller and Interrupts
Context Scheduling
Strict Priority Distributed Coordination Function in Wireless Networks
System and Related Methods to Facilitate Delivery of Enhanced Data Services in a Mobile Wireless Communications Environment
Method and Apparatus for Coalescing Two or More Transacting Requests
Method and System for Concurrent Handler Execution in an Smi and Pmi-Based Dispatch-Execution Framework
Interactive Delivery of Media Using Dynamic Playlist Generation Subject to Restrictive Criteria
Patent:
7,689,705 →
Application:
10/021,752 →
Method and System for Customized Television Viewing Using a Peer-to-Peer Network
Invoking Acpi Source Language Code from Interrupt Handler
Hot Plug Interface Control Method and Apparatus
Secure Delivery of Encrypted Digital Content
Method and Apparatus for Increasing Spectral Efficiency Using Mitigated Power Near Band-Edge
Patent:
7,151,795 →
Application:
10/036,779 →
Method and Apparatus to Manage Use of System Power Within a Given Specification
Memory Bus Termination with Memory Unit Having Termination Control
Removable Customizable Inserts and Faceplate for Electronic Devices
Parallel Processor with Functional Pipeline Providing Programming Engines by Supporting Multiple Contexts and Critical Section
Low Cost Built-in Self Test State Machine for General Purpose Ram Testing
Automatic Power Down
Method and Apparatus for Loading a Trustable Operating System
Interface Engine Providing a Continuous User Interface
Method and Apparatus for Connecting Packet Telephony Calls Between Secure and Non-Secure Networks
Dynamic Voltage Scaling Scheme for an on-Die Voltage Differentiator Design
Memory System with Burst Length Shorter Than Prefetch Length
Enabling Online and Offline Operation
Anticipation of Communications Connectivity Changes for Mobile Devices
System and Method for Execution of a Secured Environment Initialization Instruction
Peer-To-Peer Bus Segment Bridging
Registers for Data Transfers
Method of Providing Adaptive Security
Selectable Clocking Synchronization of a Parallel-to-Serial Converter and Memory
Hardened Extensible Firmware Framework
Validation of Inclusion of a Platform Within a Data Center
Method and Apparatus for Time Domain Equalization
Asynchronous Crossbar with Deterministic or Arbitrated Control
Providing Overload Protection in Battery Operation
Method and System for Multiple Channel Wireless Transmitter and Receiver Phase and Amplitude Calibration
Managing User Interface Data on Wireless Devices
System and method for protection against untrusted system management code by redirecting a system management interrupt and creating a virtual machine container
Application:
10/165,597 →
Publication:
US 2003/0229794
Transcoding Media Content from a Personal Video Recorder for a Portable Device
Method of Confirming a Secure Key Exchange
Method and Apparatus to Permit External Access to Internal Configuration Registers
System and Method for a Shared I/O Subsystem
Dynamic Configuration of Network Data Flow Using a Shared I/O Subsystem
System and Method for Implementing Lan Within Shared I/O Subsystem
Network Data Flow Optimization
System and Method for Implementing Virtual Adapters and Virtual Interfaces in a Network System
Selection of User-Specific Transmission Parameters for Optimization of Transmit Performance in Wireless Communications Using a Common Pilot Channel
Patent:
7,342,912 →
Application:
10/187,026 →
Beam Forming and Transmit Diversity in a Multiple Array Radio Communications System
Patent:
7,372,911 →
Application:
10/187,231 →
Method and Apparatus to Process Switch Traffic
Shifted Training Sequences in a Communications System
Prevention of Denial of Service Attacks
Apparatus and Methods for Providing Enhanced Redundancy for an on-Die Cache
Secure Method to Perform Computer System Firmware Updates
Method and Apparatus for Resizing Video Content Displayed Within a Graphical User Interface
Logarithmic Time Range-Based Multifield-Correlation Packet Classification
Fusion of Processor Micro-Operations
Memory Device, Circuits and Methods for Operating a Memory Device
Cache Management
Network Protocol Engine
Asynchronous Crossbar with Deterministic or Arbitrated Control
Asynchronous Crossbar with Deterministic or Arbitrated Control
Operating System-Independent Method and System of Determining Cpu Utilization
Method and Apparatus for Forming Metal-Metal Oxide Etch Stop/Barrier for Integrated Circuit Interconnects
Limit Interface for Performance Management
Method and System for Reducing Congestion in Computer Networks
Patent:
6,886,141 →
Application:
10/266,360 →
Determining Network Path Transmission Unit
Method for Making a Dual Damascene Interconnect Using a Dual Hard Mask
System and Method for Implementing an Adaptive Replacement Cache Policy
Methods and Apparatus for Controlling an Electronic Device
Managing a Protocol Control Block Cache in a Network Device
Embedded Transport Acceleration Architecture
Interface Accelerator
Interconnecting Network Processors with Heterogeneous Fabrics
Control of Voltage Regulator Thermal Condition
Method and Apparatus for Multimedia Communication Over Packet Channels
Method and System for Guaranteeing Quality of Service in a Multi-Plane Cell Switch
Method and Apparatus for Ensuring Cell Ordering in Large Capacity Switching Systems and for Synchronizing the Arrival Time of Cells to a Switch Fabric
Non-Speculative Distributed Conflict Resolution for a Cache Coherency Protocol
Adaptive Frequency Clock Signal
Methods and Apparatus to Control Power State Transitions
Integrating N-Type and P-Type Metal Gate Transistors
Method of Addressing Individual Memory Devices on a Memory Module
Communication Subsystem for Wireless Devices or the Like
Refresh Port for a Dynamic Memory
Network Protocol Off-Load Engines
Method and Apparatus for Strong Authentication and Proximity-Based Access Retention
Method and Apparatus for Distributing Notification Among Cooperating Devices and Device Channels
Heat Sink Attachment Device
Virtual Output Queue (Voq) Management Method and Apparatus
Method for Making a Semiconductor Device Having a High-K Gate Dielectric
Patent:
6,709,911 →
Application:
10/338,174 →
Weighted Fair Share Scheduler for Large Input-Buffered High-Speed Cross-Point Packet/Cell Switches
Power/Performance Optimized Memory Controller Considering Processor Power States
Method and Apparatus for Memory Management
Secondary Touch Contextual Sub-Menu Navigation for Touch Screen Interface
Method and System for Data Management in a Video Decoder
Patent:
7,672,372 →
Application:
10/374,777 →
Four-color mosaic pattern for depth and image capture
Application:
10/376,156 →
Publication:
US 2004/0174446
Method and Apparatus to Steer Memory Access Operations in a Virtual Memory System
Patent:
6,912,644 →
Application:
10/383,082 →
Method for Making a Semiconductor Device Having a High-K Gate Dielectric
Patent:
6,716,707 →
Application:
10/387,303 →
System and Method for the Distribution of Software Products
Method for Making a Semiconductor Device Having a High-K Gate Dielectric
Patent:
6,696,327 →
Application:
10/391,816 →
Forming a Porous Dielectric Layer
Patent:
6,737,365 →
Application:
10/395,447 →
Robust Variable Keeper Strength Process-Compensated Dynamic Circuit and Method
Two-Phase Cooling Utilizing Microchannel Heat Exchangers and Channeled Heat Sink
Micro-Channel Heat Exchangers and Spreaders
Cache allocation
Application:
10/406,798 →
Publication:
US 2004/0199727
Machine Learning
Heatsink Assembly
Speculative Multi-Threading for Instruction Prefetch and/or Trace Pre-Build
Template-Based Map Distribution System
Navigation System Using Corridor Maps
Dynamic Navigation System
Method for Making a Semiconductor Device Having a Metal Gate Electrode
Sliding Screen Emerging Keyboard
Apparatus and Method of Memory Access Control for Bus Masters
Integrated Circuit Capable of Communicating Using Different Communication Protocols
Method and System for Maintaining Partial Order of Packets
Power Delivery Through a Flex Tape in Decoupled I/O-Power Hybrid Substrate
Stacked Device Underfill and a Method of Fabrication
Memory Channel Having Deskew Separate from Redrive
Memory Channel with Bit Lane Fail-Over
Method to Dynamically Optimize the Power Efficiency of a Display Backlighting System Based on the Output Load
Method and Apparatus for Detecting Interruption of an Input Signal with Cancellation of Offset Level
Architecture and Method for Framing Control and Data Bursts Over 10 Gbit Ethernet with and Without Wan Interface Sublayer Support
Gate-Induced Strain for Mos Performance Improvement
Provisioning for a Modular Server
Apparatus and Method Extending Flip-Chip Pad Structures for Wirebonding on Low-K Dielectric Silicon
Method for Data Transmission Within a Wireless Local Area Network
Data Switch and Method of Operating the Data Switch
Power Reduction in Switch Architectures
Low Density Parity Check (Ldpc) Code Decoder
Leakage Power Estimation
Processor to Processor Communication in a Data Driven Architecture
Method of Forming a Stacked Device Filler
Method and Apparatus for Improving the Upstream Data Transfer Rate for a Cable Modem
System and method for prioritizing data transmission and transmitting scheduled wake-up times to network stations based on downlink transmission duration
Cascaded Phase-Locked Loops
Thermal Interface Structure with Integrated Liquid Cooling and Methods
Nonplanar Semiconductor Device with Partially or Fully Wrapped Around Gate Electrode and Methods of Fabrication
Method and System for a Network Node for Attachment to Switch Fabrics
Adaptive Guard Intervals in Ofdm Systems
Pseudo-Dynamic Latch Deracer
Queued Locks Using Monitor-Memory Wait
Solder Interface Locking Using Unidirectional Growth of an Intermetallic Compound
System and Method for Dynamically Configuring and Transitioning Wired and Wireless Networks
Reference Voltage Generator
Method for Transcoding Mpeg Encoded Streams
Method and Apparatus for Partial Refreshing of Drams
Air Gap Integration
Sense Amplifier with Reduced Detection Error
Methods and Apparatus for Asserting Flow Control at Input Ports of a Shared-Memory Switch
Power Supply Voltage Droop Compensated Clock Modulation for Microprocessors
Method of Fabricating an Ultra-Narrow Channel Semiconductor Device
Subscription Management
Safe Store for Speculative Helper Threads
Use of Global Positioning Satellites (Gps) to Discover and Select Local Services
Read Bias Scheme for Phase Change Memories
Lateral Phase Change Memory
Low Power Circuits with Small Voltage Swing Transmission, Voltage Regeneration, and Wide Bandwidth Architecture
Method, Apparatus and System for Accessing Multiple Nodes on a Private Network
Method and System for Authenticating a User of a Computer System That Has a Trusted Platform Module (Tpm)
Electronic Programming Guide with Selectable Categories
Transition Metal Alloys for Use as a Gate Electrode and Devices Incorporating These Alloys
Storing Encrypted and/or Compressed System Context Information When Entering a Low-Power State
Scalable Device-to-Device Interconnection
Polymer Memory Having a Ferroelectric Polymer Memory Material with Cell Sizes That Are Asymmetric
Hardware Recovery in a Multi-Threaded Architecture
Method and Apparatus for Efficient Utilization for Prescient Instruction Prefetch
Thick Metal Layer Integrated Process Flow to Improve Power Delivery and Mechanical Buffering
Synchronizing Use of a Device by Multiple Software Components in Accordance with Information Stored at the Device
Extended Stand Computer System with Retractable Keyboard
Four-Color Mosaic Pattern for Depth and Image Capture
Methods of Forming Backside Connections on a Wafer Stack
Designs and Methods for Conductive Bumps
Method and Apparatus for Fast Lock Acquisition in Self-Biased Phase Locked Loops
System and Method for Grouping Processors and Assigning Shared Memory Space to a Group in Heterogeneous Computer Environment
Stitched Micro-via to Enhance Adhesion and Mechanical Strength
Virtual Management Controller to Coordinate Processing Blade Management in a Blade Server Environment
High-Speed Data Sampler for Optical Interconnect
Switching Between a Service Virtual Machine and a Guest Virtual Machine in a Virtual Machine Monitor Environment
Method and Apparatus for Selective Dram Precharge
Switching Display Update Properties Upon Detecting a Power Management Event
Coordinating Backlight Frequency and Refresh Rate in a Panel Display
Method and Apparatus for Improving Stability of a 6T Cmos Sram Cell
Deposition of Diffusion Barrier
Multi-Sense Voltage Regulator
Epitaxially Deposited Source/Drain
Method for Making a Semiconductor Device Having Increased Conductive Material Reliability
Cooling System for an Electronic Component
Method for Making a Semiconductor Device Having a Metal Gate Electrode
Method, System, and Program for Interfacing with a Network Adaptor Supporting a Plurality of Devices
Method and System Performing Concurrently Mark-Sweep Garbage Collection Invoking Garbage Collection Thread to Track and Mark Live Objects in Heap Block Using Bit Vector
Virtual Direct Memory Acces Crossover
System and Method for Soft Error Handling
Time-Controlled Messaging System
Patent:
7,224,777 →
Application:
10/727,177 →
Stackable Integrated Circuit Packaging
System and Method for Channelization Recognition in a Wideband Communication System
Method of Forming a Stacked Device Filler
User-Programmable Low-Overhead Multithreading
Handoff Apparatus, Systems, and Methods
Performance Monitoring Based Dynamic Voltage and Frequency Scaling
Dynamically Setting Routing Information to Transfer Input Output Data Directly into Processor Caches in a Multi Processor System
Register Alias Table Cache to Map a Logical Register to a Physical Register
Static Random Access Memory Having Leakage Reduction Circuit
Patent:
6,876,571 →
Application:
10/738,220 →
Computer System Maintenance and Diagnostics Techniques
Resource Partitioning and Direct Access Utilizing Hardware Support for Virtualization
Method and Apparatus to Generate a Reference Value in a Memory Array
Packet Classification
Program Clock Synchronization in Multimedia Networks
Interfacing a Digital Display Card Through Pci Express Connector
Methods and Apparatuses to Provide Message Signaled Interrupts to Level-Sensitive Drivers
Switching Device Utilizing Internal Priority Assignments
Methods of Processing Thick Ild Layers Using Spray Coating or Lamination for C4 Wafer Level Thick Metal Integrated Flow
Unified Memory Organization for Power Savings
Transistor Gate Electrode Having Conductor Material Layer
Method of Fabricating Semiconductor Devices with Replacement, Coaxial Gate Structure
Damascene Process for Fabricating Interconnect Layers in an Integrated Circuit
System and Method for Providing Usage Metrics of Digital Content
Method for Making a Semiconductor Device Having a High-K Gate Dielectric
Methods for Integrating Replacement Metal Gate Structures
Monitoring Packet Flows
Filling the space-time channels in SDMA
Application:
10/749,293 →
Publication:
US 2005/0141495
Anycast Addressing for Internet Protocol Version Six
Intermediate Device Capable of Communicating Using Different Communication Protocols
Integrated Micro Channels and Manifold/Plenum Using Separate Silicon or Low-Cost Polycrystalline Silicon
Multichannel Orthogonal Frequency Division Multiplexed Receivers with Antenna Selection and Maximum-Ratio Combining and Associated Methods
Nonplanar Transistors with Metal Gate Electrodes
Method and Apparatus to Counter Mismatched Burst Lengths
Controlled Faceting of Source/Drain Regions
Symbol De-Mapping Methods in Multiple-Input Multiple-Output Systems
Method for Signaling Pci/Pci-X Standard Hot-Plug Controller (Shpc) Command Status
Apparatus and Associated Methods to Perform Space-Frequency Interleaving in a Multicarrier Wireless Communication Channel
Extended Stand Computer System with Non-Retractable Carrying Handle
Multiple-Antenna Communication Systems and Methods for Communicating in Wireless Local Area Networks That Include Single-Antenna Communication Devices
Tri-Gate Transistors and Methods to Fabricate Same
Protecting an Operating System Kernel from Third Party Drivers
Method for making a semiconductor device having a high-k gate dielectric
Application:
10/771,267 →
Publication:
US 2004/0180523
Codec Control
Variable Impedance Output Driver
Patent:
7,084,662 →
Application:
10/773,816 →
Method and Apparatus for Managing Buffers in Pci Bridges
Forming a Porous Dielectric Layer
System and Method to Exchange Information Between a Control Element and Forwarding Elements in a Network Element Architecture
Interchangeable connection arrays for double-sided memory module placement
Application:
10/792,350 →
Publication:
US 2005/0195629
Method and Apparatus for Managing Access to Stored Objects Based on Retention Policy
System and Method for Uninterrupted Streaming
Patent:
7,925,771 →
Application:
10/793,018 →
Microprocessor Die with Integrated Voltage Regulation Control Circuit
Method and Apparatus for Pvt Controller for Programmable on Die Termination
Method for Making a Semiconductor Device with a Metal Gate Electrode
Patent:
6,893,927 →
Application:
10/805,880 →
Separate Thermal and Electrical Throttling Limits in Processors
Fingerprinting Digital Video for Rights Management in Networks
Method and Apparatus for Communicating Information from an Operating System Based Environment of a Server Blade to the Chassis Management Module
Power Managed Busses and Arbitration
Sram with Forward Body Biasing to Improve Read Cell Stability
Single-Stage and Multi-Stage Low Power Interconnect Architectures
Processor Control Register Virtualization to Minimize Virtual Machine Exits
Surface emitting laser with an integrated absorber
Application:
10/814,050 →
Publication:
US 2006/0029112
Stacked Device Underfill and a Method of Fabrication
Hardware-Based Multi-Threading for Packet Processing
Ofdm System with Per Subcarrier Phase Rotation
Transceiver with Calibrated I and Q Paths and Methods for Deconvolved Calibration
Apparatus and Method to Maximize Buffer Utilization in an I/O Controller
Method of Embedding Passive Component Within Via
Enhancing Strained Device Performance by Use of Multi Narrow Section Layout
Semiconducting Device with Stacked Dice
Render-Cache Controller for Multithreading, Multi-Core Graphics Processor
Semiconductor Device Having a Laterally Modulated Gate Workfunction and Method of Fabrication
Semiconductor Substrate with Interconnections and Embedded Circuit Elements
Bulk Non-Planar Transistor Having Strained Enhanced Mobility and Methods of Fabrication
Additive Digital Predistortion System Employing Parallel Path Coordinate Conversion
Network Storage Target Boot and Network Connectivity Through a Common Network Device
Method to Manage Memory in a Platform with Virtual Machines
Method of Forming Air Gaps in a Dielectric Material Using a Sacrificial Film and Resulting Structures
Method for selling content over a network
Application:
10/832,186 →
Publication:
US 2005/0240487
Transmitting Peer-to-Peer Transactions Through a Coherent Interface
Apparatus and Method Capable of Providing Quality of Service Channel Access in a Wireless Network
Rf Amplifier Employing Active Load Linearization
Docking Solution for a Tablet Notebook Computer
Methods and Apparatus for Integrity Measurement of Virtual Machine Monitor and Operating System via Secure Launch
Transcoding Media Content from a Personal Video Recorder for a Portable Device
Ping-Pong Avoidance Load Balancing Techniques and Structures for Wireless Communication
Link Power Saving State
P-State Feedback to Operating System with Hardware Coordination
Integrating N-Type and P-Type Metal Gate Transistors
Content Filtering for a Digital Audio Signal
Hardware Coordination of Power Management Activities
Metal-Metal Oxide Etch Stop/Barrier for Integrated Circuit Interconnects
Techniques for Self-Isolation of Networked Devices
Establishing a Virtual Drive Accessible to Pre-Boot and Operating System Runtime Phases
Power State Coordination Between Devices Sharing Power-Managed Resources
Method, System, and Apparatus to Decrease Cpu Temperature Through I/O Bus Throttling
Remote Audio
Biometric Identification Data Protection
Multiple Input Multiple Output Multicarrier Communication System and Methods with Quantized Beamforming Feedback
Closed-Loop Independent Dll-Controlled Rise/Fall Time Control Circuit
Closed-Loop Independent Dll-Controlled Rise/Fall Time Control Circuit
Extended Thermal Management
Power Management Apparatus, Systems, and Methods
Transistors with Increased Mobility in the Channel Zone and Method of Fabrication
Compare and exchange operation using sleep-wakeup mechanism
System and Method for Managing Power Consumption Within an Integrated Circuit
Memory Isolation and Virtualization Among Virtual Machines
Dynamic Power Requirement Budget Manager
Computing a Higher Resolution Image from Multiple Lower Resolution Images Using Model-Based, Robust Bayesian Estimation
Share Resources and Increase Reliability in a Server Environment
Accessing Phase Change Memories
An Automated Management System Generating Network Policies Based on Correlated Knowledge to Modify Operation of a Computer Network
Wafer Bondng with Highly Compliant Plate Having Filler Material Enclosed in Hollow Core.
Methods and Apparatus for Improving Impedance Tolerance of on-Die Termination Elements
Method for Making a Semiconductor Device Having a High-K Gate Dielectric Layer and a Metal Gate Electrode
Dependable Microcontroller, Method for Designing a Dependable Microcontroller and Computer Program Product Therefor
Communications Systems and Methods
Communications Systems and Methods
Mechanism for Handling Explicit Writeback in a Cache Coherent Multi-Node Architecture
bonded wafer structure with local deflection
Application:
10/898,400 →
Publication:
US 2006/0003548
Structured Integrated Circuit Device
Method and Apparatus for Dynamic Dll Powerdown and Memory Self-Refresh
Power Management Coordination in Multi-Core Processors
Non-Planar Pmos Structure with a Strained Channel Region and an Integrated Strained Cmos Flow
System and Method to Enable Processor Management Policy in a Multi-Processor Environment
Techniques to Utilize Queues for Network Interface Devices
Method to Fill the Gap Between Coupled Wafers
Power Delivery System in Which Power Supply and Load Exchange Power Consumption Measurements via Digital Bus
Formation of Air Gaps in an Interconnect Structure Using a Thin Permeable Hard Mask and Resulting Structures
Method of Forming Abrupt Source Drain Metal Gate Transistors
Dynamic Navigation System
Method for Making a Semiconductor Device Having a High-K Gate Dielectric
Method for Making a Semiconductor Device Having a High-K Gate Dielectric Layer and a Metal Gate Electrode
Operating System Independent Agent
Remotely Providing Basic Input/Output System to a Client System
Integrated Radio Front-End Module with Embedded Circuit Elements
Integrating N-Type and P-Type Metal Gate Transistors
Selection of Spawning Pairs for a Speculative Multithreaded Processor
Method and Apparatus for Run-Ahead Victim Selection to Reduce Undesirable Replacement Behavior in Inclusive Caches
Dynamic Multi-Vcc Scheme for Sram Cell Stability Control
Role-Based Network Traffic-Flow Rate Control
Frequency Management Apparatus, Systems, and Methods
Multicarrier Transmitter and Method for Transmitting Multiple Data Streams with Cyclic Delay Diversity
Floating-Body Memory Cell Write
Calibration of Thermal Sensors for Semiconductor Dies
Metal Gate Transistors with Epitaxial Source and Drain Regions
Global and Pseudo Power State Management for Multiple Processing Elements
Nonplanar Transistors with Metal Gate Electrodes
Power-Scavenging Receiver to Generate a Signal to Be Used to Control Operational State
Performance enhancement of address translation using translation tables covering large address spaces
Storage Medium for Data Backup and Method for the Same
Hardened extensible firmware framework to support system management mode operations using 64-bit extended memory mode processors
Application:
10/971,824 →
Publication:
US 2005/0114639
Pci to Pci Express Protocol Conversion
Methodology and Apparatus for Implementing Write Combining
Power consumption-based thread scheduling
Application:
10/982,613 →
Publication:
US 2006/0107262
Local and Remote Network Based Management of an Operating System-Independent Processor
System and Method for the Controlled on-Demand Distribution of Content via a Centralized Server and a Peer-to-Peer Network
Parallel-Connected Voltage Regulators for Supplying Power to Integrated Circuit So That Second Regulator Minimizes Current Output from First Regulator
Method and Apparatus for Conserving Power on a Mobile Device Through Motion Awareness
Method for forming an integrated circuit
Application:
10/993,865 →
Mobile Device and Geographic Information System Background and Summary of the Related Art
Multiple Antenna Multicarrier Communication System and Method with Reduced Mobile-Station Processing
Preventing System Snoop and Cross-Snoop Conflicts
Method and Apparatus for Optimizing Strobe to Clock Relationship
Performance State-Based Thread Management
Method for Making a Semiconductor Device Having a High-K Gate Dielectric and a Titanium Carbide Gate Electrode
Alloyed Underlayer for Microelectronic Interconnects
Packet Processing in Switched Fabric Networks
Sc Circuit Arrangement
Interleaved Boot Block to Support Multiple Processor Architectures and Method of Use
PMI loader and execution mechanism supporting extensible PMI event handlers
Application:
11/010,930 →
Publication:
US 2005/0102459
Flow Assignment
Poly Open Polish Process
Pin Multiplexing
Spatio-Temporal Adaptive Video De-Interlacing
System, Method and Device for Secure Wireless Communication
Nonplanar Transistors with Metal Gate Electrodes
Predictive Early Write-Back of Owned Cache Blocks in a Shared Memory Computer System
Dynamic Power Control for Reducing Voltage Level of Graphics Controller Component of Memory Controller Based on Its Degree of Idleness
Direct Memory Access (Dma) Address Translation Between Peer-to-Peer Input/Output (I/O) Devices
Ballout for Buffer
Method and apparatus for regulating the voltage supplied to a computer system
Application:
11/026,649 →
Publication:
US 2005/0154932
System Security Event Notification Aggregation and Non-Repudiation
Method and system for multiple channel wireless transmitter and receiver phase and amplitude calibration
Application:
11/026,949 →
Publication:
US 2005/0117677
Processor Having Content Addressable Memory for Block-Based Queue Structures
Transaction Based Shared Data Operations in a Multiprocessor Environment
Method and Apparatus for Providing a Low Power Mode for a Processor While Maintaining Snoop Throughput
Remote Direct Memory Access Segment Generation by a Network Controller
Packet Data Placement in a Processor Cache
Configuration Data Management
Multilevel Programming of Phase Change Memory Cells
Method and Apparatus for Supporting Address Translation in a Virtual Machine Environment
Methods and Apparatus for Data Communication for Mobile Electronic Devices
Semiconductor Device Having a Metal Gate Electrode
Digital Predistortion System and Method for High Efficiency Transmitters
Method of Fabricating an Ultra-Narrow Channel Semiconductor Device
Gate-Induced Strain for Mos Performance Improvement
Methods of Forming Backside Connections on a Wafer Stack
Method for Making a Semiconductor Device Having Increased Conductive Material Reliability
Forming a Barrier Layer in Interconnect Joints and Structures Formed Thereby
High Efficiency Linear Amplifier Employing Dynamically Controlled Back Off
Constant Gain Nonlinear Envelope Tracking High Efficiency Linear Amplifier
Bulk Non-Planar Transistor Having Strained Enhanced Mobility and Methods of Fabrication
Processing Packet Sequence Using Same Function Set Pipelined Multiple Threads Spanning Over Multiple Processing Engines and Having Exclusive Data Access
Decoder Architecture Systems, Apparatus and Methods
Temperature Determination and Communication for Multiple Devices of a Memory Module
Platform Configuration Register Virtualization Apparatus, Systems, and Methods
Credit-Based Activity Regulation Within a Microprocessor Based on an Allowable Activity Level
Transitioning Between Virtual Machine Monitor Domains in a Virtual Machine Environment
Bio-Metric Input Mechanism
System and Method for Execution of a Secured Environment Initialization Instruction
Temperature-based thread scheduling
Apparatus for Determining Temperature of a Portable Computer System
Semiconductor Device Having a Laterally Modulated Gate Workfunction and Method of Fabrication
Spectral Shaping for Multiband Ofdm Transmitters with Time Spreading
Patent:
7,519,123 →
Application:
11/099,224 →
Silicon-Doped Carbon Dielectrics
Offloading Data Path Functions
An Apparatus and Method Having a Virtual Bridge to Route Data Frames
Methods and Apparatus to Facilitate Fast Restarts in Processor Systems
Automated Notification Systems and Methods
Memory Device, Circuits and Methods for Operating a Memory Device
Simulating Multiple Virtual Channels in Switched Fabric Networks
Mobile Systems with Seamless Transition by Activating Second Subsystem to Continue Operation of Application Executed by First Subsystem as It Enters into Sleep Mode
Radio Resource Measurement and Estimation
Methods of Forming Electromigration and Thermal Gradient Based Fuse Structures
Memory with Dynamically Adjustable Supply
Token Id Mechanism for Network Data Transfer
Patent:
7,804,862 →
Application:
11/137,920 →
Protocol to Implement Token Id Mechanism for Network Data Transfer
Patent:
7,561,567 →
Application:
11/137,925 →
Cut-Through Decode and Reliability
Patent:
7,889,749 →
Application:
11/137,980 →
Partial Page Scheme for Memory Technologies
Method, Apparatus, Article and System for Use in Association with Images
Context scheduling
Application:
11/141,993 →
Publication:
US 2006/0026596
Capping Copper Bumps
Electronic Packaging Including Die with Through Silicon Via
Interconnects Having Sealing Structures to Enable Selective Metal Capping Layers
Wireless Medical Sensor System
Method and Apparatus to Reduce Latency and Improve Throughput of Input/Output Data in a Processor
System and Method for Adaptively Managing Pages in a Memory
Memory Attribute Speculation
Reducing Computing System Power Through Idle Synchronization
Method for Fabricating Transistor with Thinned Channel
Automated Bist Execution Scheme for a Link
Methods for Patterning a Semiconductor Film
Memory Device Identification
Primitives to Enhance Thread-Level Speculation
Non-Speculative Distributed Conflict Resolution for a Cache Coherency Protocol
Method and Apparatus for Improving Stability of a 6T Cmos Sram Cell
Grid Array Connection Device and Method
Packaging logic and memory integrated circuits
Application:
11/168,784 →
Publication:
US 2006/0289981
Processor Power Management Associated with Workloads
Low-Voltage, Buffered Bandgap Reference with Selectable Output Voltage
Method and Apparatus for Migrating Software-Based Security Coprocessors
Power Prioritization Among Functions of a Multi-Function Device
Protocol Agnostic Switching
Method and Apparatus for Remotely Provisioning Software-Based Security Coprocessors
Apparatus and Method Extending Flip-Chip Pad Structures for Wirebonding on Low-K Dielectric Silicon
Multi-Pattern Packet Content Inspection Mechanisms Employing Tagged Values
Power Management System for Computing Platform
Transistor with Improved Tip Profile and Method of Manufacture Thereof
Method and Apparatus to Calibrate Dram on Resistance (Ron) and on-Die Termination (Odt) Values Over Process, Voltage and Temperature (Pvt) Variations
Various Apparatuses and Methods for Reduced Power States in System Memory
Nanotube-And Nanocrystal-Based Non-Volatile Memory
Identifying and Accessing Individual Memory Devices in a Memory Channel
Stateful Packet Content Matching Mechanisms
Low Speed Access to Dram
Tools for Accessing Digital Works
Interface Engine Providing a Continuous User Interface
Radio Frequency Identification Tags Capable of Embedding Receiver Signal Strength Indications
Structured Integrated Circuit Device
Hardware Management Module
Transition Metal Alloys for Use as a Gate Electrode and Devices Incorporating These Alloys
Lateral Undercut of Metal Gate in Soi Device
Shared-Memory Switch Fabric Architecture
Method for Making a Semiconductor Device Having a High-K Gate Dielectric
Interpreting Visual Imagery for Providing Context-Based Information Services
Application:
11/215,601 →
Publication:
US 2006/0047704
Methods for integrating replacement metal gate structures
Application:
11/218,355 →
Publication:
US 2006/0008954
Network load balancing apparatus, systems, and methods
Application:
11/219,528 →
Publication:
US 2007/0053294
Mulit-Layered Interconnect Structure
Application:
11/221,453 →
Publication:
US 2006/0012039
Method for Setting an Amplifier, and Corresponding Amplifier Circuit
Dynamically Configuring a Video Decoder Cache for Motion Compensation
Multi Mode Clock Generator
Trusted Platform Module for Generating Sealed Data
CMOS devices with a single work function gate electrode and method of fabrication
Application:
11/238,447 →
Publication:
US 2007/0090416
Reliable Computing with a Many-Core Processor
Apparatus, System, and Method for Persistent User-Level Thread
Methods and Arrangements to Remap Degraded Storage Blocks
Dual Gate Oxide One Time Programmable (Otp) Antifuse Cell
Dma Descriptor Management Mechanism
Instruction-Assisted Cache Management for Efficient Use of Cache and Memory
Power Sequencing
Integrated Circuit Communication Techniques
Integrating N-Type and P-Type Metal Gate Transistors
Low Power Circuits with Small Voltage Swing Transmission, Voltage Regeneration and Wide Bandwidth Architecture
Method for Making a Semiconductor Device Having a High-K Gate Dielectric and a Titanium Carbide Gate Electrode
Method and apparatus to permit external access to internal configuration registers
Application:
11/263,038 →
Publication:
US 2006/0075177
Passive Thermal Solution for Hand-Held Devices
Power Reducing Logic and Non-Destructive Latch Circuits and Applications
Thick metal layer integrated process flow to improve power delivery and mechanical buffering
Application:
11/281,709 →
Publication:
US 2006/0076678
3D Integrated Circuits Using Thick Metal for Backside Connections and Offset Bumps
Integrated Micro Channels and Manifold/Plenum Using Separate Silicon or Low-Cost Polycrystalline Silicon
Novel Transmitter Architecture for High-Speed Communications
System and Method for the Prevention of Display Burn-In
Component Reliability Budgeting System
Dynamic on-Die Termination Launch Latency Reduction
System and Method for Controlling Home Network Devices Using Multicast Enabled Remote Controls
Apparatus and Method for Thermal Management of a Memory Device
Apparatus and Method for Impedance Matching in a Backplane Signal Channel
Single-Stage and Multi-Stage Low Power Interconnect Architectures
Cache Disassociation Detection
Graphics Processing on a Processor Core
Clock Deskewing Method, Apparatus, and System
Receive Clock Deskewing Method, Apparatus, and System
Using Asymmetric Lanes Dynamically in a Multi-Lane Serial Link
Method and Apparatus for Utilizing Platform Support for Direct Memory Access Remapping by Remote Dma ("Rdma")-Capable Devices
Load Adaptive Power Delivery
Fine Granularity Dram Refresh
Patent:
7,221,609 →
Application:
11/321,367 →
Computing a higher resoultion image from multiple lower resolution images using model-based, robust bayesian estimation
Application:
11/321,580 →
Publication:
US 2006/0104540
Stacked Die Semiconductor Package
Method and Apparatus to Adjust Voltage for Storage Location Reliability
Memory Power Delivery Noise Suppression
Dividing a Flash Memory Operation into Phases
Load Mechanism
Method and Apparatus for a Zero Voltage Processor Sleep State
Monitor Implementation in a Multicore Processor with Inclusive Llc
Error-Detection Flip-Flop
Chip-Spacer Integrated Radio Frequency Id Tags, Methods of Making Same, and Systems Containing Same
Locally Asynchronous, Block-Level Synchronous, Configurable Logic Blocks with Sub-Threshold Analog Circuits
Clock-Gated Random Access Memory
Abrupt Junction Formation by Atomic Layer Epitaxy of in Situ Delta Doped Dopant Diffusion Barriers
Apparatus and Method for Protection of Management Frames
Hybrid Image and Movie Imaging System and Method
Method for Forming an Integrated Circuit
Pvt Controller for Programmable on Die Termination
Network Load Balancing
Structured Integrated Circuit Device
Method and Apparatus for Using a Single Multi-Function Adapter with Different Operating Systems
Memory Replay Mechanism
Thermal Management Using an on-Die Thermal Sensor
Using Unstable Nitrides to Form Semiconductor Structures
Method of Forming Air Gaps in a Dielectric Material Using a Sacrificial Film and Resulting Structures
Thermal Interface Structure with Integrated Liquid Cooling and Methods
Method of Forming Metal Gate Electrodes Using Sacrificial Gate Electrode Material and Sacrificial Gate Dielectric Material
Thermal Interface Structure with Integrated Liquid Cooling and Methods
A Method of Forming a Metal Oxide Dielectric
Structured Integrated Circuit Device
Rf Amplifier Employing Active Load Linearization
Forming a Hybrid Device
Method for Making a Semiconductor Device Having a High-K Gate Dielectric
Processor with Configurable Association Between Interface Signal Lines and Clock Domains
Performance State Management
Coordinated Transmissions in Wireless Networks
Systems for Communicating Using Multiple Frequency Bands in a Wireless Network
Single Package Wireless Communication Device
Embedding Device in Substrate Cavity
Image Buffering Techniques
Balancing power supply and demand
Application:
11/395,677 →
Publication:
US 2007/0229024
Switch-Based Network Processor
Uniform Silicide Metal on Epitaxially Grown Source and Drain Regions of Three-Dimensional Transistors
Capillary Underfill of Stacked Wafers
Buffered Cascode Current Mirror
Platform configuration apparatus, systems, and methods
Application:
11/396,266 →
Publication:
US 2007/0056033
Epitaxially deposited source/drain
Application:
11/408,133 →
Publication:
US 2006/0197164
System and Method for Allocating and Deallocating Memory Within Transactional Code
Method and System for Managing Multimedia Documents
Application:
11/423,234 →
Publication:
US 2006/0218191
Method and System for Providing Information Services Related to Multimodal Inputs
Information Services for Real World Augmentation
Application:
11/423,252 →
Publication:
US 2006/0230073
User Interface for Multimodal Information System
Multimodal Context Marketplace
Dielectric Spacers for Metal Interconnects and Method to Form the Same
Method and an Apparatus to Sense Supply Voltage
Load Circuit Supply Voltage Control
Mechanism to Flexibly Support Multiple Device Numbers on Point-to-Point Interconnect Upstream Ports
Power Control Unit with Digitally Supplied System Parameters
Polymer Memory Having a Ferroelectric Polymer Memory Material with Cell Sizes That Are Asymmetric
Enhancing Strained Device Performance by Use of Multi Narrow Section Layout
Strain-Inducing Semiconductor Regions
Low-Power Battery Pack with Hall-Effect Sensor
Methods for Providing Information Services Related to Visual Imagery
Yield-Enhancing Device Failure Analysis
Low Power/Zero-Offset Charge Pump Circuits for Dlls and Plls
Method for Discovering and Partitioning Pci Devices
Method, system, and apparatus for dynamic thermal management
Application:
11/476,955 →
Publication:
US 2008/0005591
Amplifier Circuit with Cross-Coupled Cascode Transistors
Handling Address Translations and Exceptions of a Heterogeneous Resource of a Processor Using Another Processor Resource
Method, Apparatus, and System for Increasing Single Core Performance in a Multi-Core Microprocessor
Method and Apparatus for Redirection of Machine Check Interrupts in Multithreaded Systems
Method and System for the Protected Storage of Downloaded Media Content via a Virtualized Platform
Quantifying Core Reliability in a Multi-Core System
Method, System, and Apparatus for Dynamic Clock Adjustment
Method of confirming a secure key exchange
Application:
11/479,747 →
Publication:
US 2006/0245590
Method and Apparatus for User-Activity-Based Dynamic Power Management and Policy Creation for Mobile Platforms
Computing a Higher Resolution Image from Multiple Lower Resolution Images Using Model-Base, Robust Bayesian Estimation
Power Supply Voltage Droop Compensated Clock Modulation for Microprocessors
Data Classification in Shared Cache of Multiple-Core Processor
Voltage Regulation for a Computer System Providing Voltage Positioning for Multi-Component Load
Methods and Apparatus for Providing a Handover Control System Associated with a Wireless Communication Network
Method and Apparatus for Improving Stability of a 6T Cmos Sram Cell
Network-Like Communication and Stack Synchronization for Different Virtual Machines on the Same Physical Device
Patent:
7,346,909 →
Application:
11/511,695 →
Method and Apparatus for Migrating Virtual Trusted Platform Modules
Group Ii Element Alloys for Protecting Metal Interconnects
Dielectric Spacers for Metal Interconnects and Method to Form the Same
Method and Apparatus for User-Activity-Based Dynamic Power Management and Policy Creation for Mobile Platforms
Dual Crystal Orientation Circuit Devices on the Same Substrate
Methods and System for Providing Information Services Related to Visual Imagery Using Cameraphones
Application:
11/530,449 →
Publication:
US 2007/0002077
Methods and System for Distributed E-commerce
Application:
11/530,451 →
Publication:
US 2007/0005490
Methods and Apparatus to Self-Initialize a Processor
Subsystem Power Management
System and Method for Providing Digital Content on Mobile Devices
Application:
11/539,634 →
Publication:
US 2007/0079383
Methods for Inducing Strain in Non-Planar Transistor Structures
Resolving False Dependencies of Speculative Load Instructions
Dual Clock Domain Deskew Circuit
Controls and indicators with on-screen cognitive aids
Memory Device, Circuits and Methods for Reading a Memory Device
Pll with Controllable Bias Level
Reconfigurable Simd Vector Processing System
Acceleration of Packet Flow Classification in a Virtualized System
Memory Module Thermal Management
Transducer Access Point
Vertical Handover Composite Quality Measures
Method and Apparatus for Increasing Spectral Efficiency Using Mitigated Transmit Power Near Band-Edge
Nanotube- and Nanocrystal-Based Non-Volatile Memory
Frequency Multiplying Delay-Locked Loop
Methods of Forming Electromigration and Thermal Gradient Based Fuse Structures
Reducing the Format Time for Bit Alterable Memories
System and Method for Aggregating Core-Cache Clusters in Order to Produce Multi-Core Processors
Lateral Phase Change Memory
Method and apparatus for combining broadcast schedules and content on a digital broadcast-enabled client platform
Application:
11/606,716 →
Publication:
US 2007/0079324
Multilevel Programming of Phase Change Memory Cells
Enabling Online and Offline Operation
Enabling Online and Offline Operation
Sleep Transistor Array Apparatus and Method with Leakage Control Circuitry
Optimizing Power Usage by Processor Cores Based on Architecutral Events
Forming a Barrier Layer in Joint Structures
Application:
11/627,812 →
Publication:
US 2007/0123025
Power Supply Circuit for a Phase-Locked Loop
Novel Fuse Programming Schemes for Robust Yield
Techniques to Share Multimedia and Enable Cellular Phone Conference Calling Using Ad-Hoc Wireless Networks
Transition metal alloys for use a gate electrode and device incorporating these alloys
Application:
11/640,034 →
Publication:
US 2007/0096163
Stacked-Die Packages with Silicon Vias and Surface Activated Bonding
High Performance Raid-6 System Architecture with Pattern Matching
Vgs Replication Apparatus, Method, and System
Electrical Signal Duty Cycle Modification
Platform Management Processor Assisted Resume
Queue Management Mechanism in Network Processor Wherein Packets Stored at Memory Device Corresponds to Addresses Stored in Plurity of Queues Within Queue Management
Method and sytem for telecine detection and restoration
Tunable Gate Electrode Work Function Material for Transistor Applications
Cmos Devices with a Single Work Function Gate Electrode and Method of Fabrication
Switched Capacitor Converters
Carbon Nanotube Coated Capacitor Electrodes
Method and Apparatus for Dynamic Voltage and Frequency Scaling
Meeting Point Thread Characterization
Transistor Gate Electrode Having Conductor Material Layer
Removalbe customizable inserts and faceplate for electronic devices
Application:
11/716,087 →
Publication:
US 2007/0161421
Queued Locks Using Monitor-Memory Wait
Power Reduction for System on Chip
Selectively Supporting Different Memory Technologies on a Single Motherboard
Variable Gain Amplifier
Surface Emitting Laser with an Integrated Absorber
Using a Live Operating System to Set Up and Configure an Active Management Technology Device
Dynamic Quality of Service (Qos) for a Shared Cache
Adjusting Pll/Analog Supply to Track Cpu Core Supply Through a Voltage Regulator
Phase Change Memory with Program/Verify Function
Forming a Non-Planar Transistor Having a Quantum Well Channel
Localized Spacer for a Multi-Gate Transistor
Transistor Having Tensile Strained Channel and System Including Same
Capacitor, Method of Increasing a Capacitance Area of Same, and System Containing Same
Optical Universal Serial Bus (Usb)
Structured Integrated Circuit Device
Methods of Processing Thick ILD Layers Using Spray Coating or Lamination for C4 Wafer Level Thick Metal Integrated Flow
Application:
11/740,246 →
Publication:
US 2007/0190776
Multi-Die Molded Substrate Integrated Circuit Device
High-Linearity Low Noise Amplifier and Method
Dynamic Power Control for Reduced Voltage Level of Graphics Controller Component of Memory Controller Based on Its Degree of Ideleness
Dynamically Setting Routing Information to Transfer Input Output Data Directly into Processor Caches in a Multi Processor System
Stitched Micro-via to Enhance Adhesion and Mechanical Strength
Multi-Chip Packaging Using an Interposer Such as a Silicon Based Interposer with Through-Silicon-Vias
Multi-Chip Packaging Using an Interposer with Through-Vias
Systems, Methods, and Apparatuses for Transmitting Data Mask Bits to a Memory Device
Microprocessor Die with Integrated Voltage Requlation Control Circuit
Method for Selling Content Over a Network
Single via Structured Ic Device
Method for Optimizing Virtualization Technology and Memory Protections Using Processor-Extensions for Page Table and Page Directory Striping
Memory Link Training
Reduced Signal Level Support for Memory Devices
Method and Apparatus to Enable Runtime Processor Migration with Operating System Assistance
Floating Body Memory Array
Memory Including Bipolar Junction Transistor Select Devices
Temperature Determination and Communication for Multiple Devices of a Memory Module
Communicating Graphics Data via an Out of Band Channel
Streaming Mode Programming in Phase Change Memories
Biasing a Phase Change Memory Device
Mobile Device and Geographic Information System Background and Summary of the Related Art
Die Backside Metallization and Surface Activated Bonding for Stacked Die Packages
Tri-Gate Transistors and Methods to Fabricate Same
Application:
11/828,290 →
Publication:
US 2007/0262389
Method and Apparatus for Distributing Notification Among Cooperating Devices and Device Channels
Link Interface Technique Including Data Indicator Symbols
Symbol De-Mapping Methods in Multiple-Input Multiple-Output Systems
Highly Compliant Plate for Wafer Bonding
Application:
11/844,293 →
Publication:
US 2007/0284409
Highly Compliant Plate for Wafer Bonding
Application:
11/844,295 →
Publication:
US 2007/0287263
Thermally and Electrically Conductive Structure, Method of Applying a Carbon Coating to Same, and Method of Reducing a Contact Resistance of Same
Method of Embedding Passive Component Within Via
Device, System, and Method of Power Saving in Wireless Network
Routing Messages Using Presence Information
Application:
11/852,972 →
Publication:
US 2007/0299927
Method, Apparatus and System for Optimizing Packet Throughput for Content Processing Systems on Chips
Embedded Power Gating
Reading Phase Change Memories with Select Devices
Designs and Methods for Conductive Bumps
Interchangeable Connection Arrays for Double-Sided Dimm Placement
Bandwidth Allocation for Network Packet Traffic
Interleaved Array Architecture
Adaptive Wordline Programming Bias of a Phase Change Memory
Queued Locks Using Monitor-Memory Wait
Generating Reference Currents Compensated for Process Variation in Non-Volatile Memories
Programming a Phase Change Memory
Programming a Multilevel Phase Change Memory Cell
Power Management of Low Power Link States
Writing Bit Alterable Memories
Integrated Circuit and Process for Fabricating Thereof
Fingerprinting Digital Video for Rights Management in Networks
Method and Apparatus for a Zero Voltage Processor Sleep State
Method, Apparatus, and System for Optimizing Frequency and Performance in a Multi-Die Microprocessor
Reliability, Availability, and Serviceability Solutions for Memory Technology
Method and System for Reliable Multicast
Patent:
7,936,753 →
Application:
11/948,897 →
Link Power Saving State
Application:
11/949,770 →
Publication:
US 2008/0077814
Link Power Saving State
Link Power Saving State
Application:
11/950,314 →
Publication:
US 2008/0075107
Using Controlled Bias Voltage for Data Retention Enhancement in a Ferroelectric Media
Method and Apparatus for Cost and Power Efficient, Scalable Operating System Independent Services
Audio Subsystem Sharing in a Virtualized Environment
Mixing Instructions with Different Register Sizes
Compressed Instruction Format
Method and System for Handling a Management Interrupt Event in a Multi-Processor Computing Device
Multi-Core Processor and Method of Communicating Across a Die
Short Circuit Detection for Batteries
Methods and Apparatuses for Flushing Write-Combined Data from a Buffer
System and Method to Establish and Dynamically Control Energy Consumption in Large-Scale Datacenters or It Infrastructures
Using a Processor Identification Instruction to Provide Multi-Level Processor Topology Information
Vector Shuffle Instructions Operating on Multiple Lanes Each Having a Plurality of Data Elements Using a Common Set of Per-Lane Control Bits
Bidirectional Power Management Techniques
Radio Frequency Identification Tags Adapted for Localization and State Indication
Device, System, and Method of Establishing Multiple Wireless Connections
Rfid Enabled Light Switches
Simultaneous Multi-Voltage Rail Voltage Regulation Messages
Forming Inductor and Transformer Structures with Magnetic Materials Using Damascene Processing for Integrated Circuits
Nonplanar Transistors with Metal Gate Electrodes
Predicting Future Power Level States for Processor Cores
Non-Planar Pmos Structure with a Strained Channel Region and an Integrated Strained Cmos Flow
Accelerating Input/Output (Io) Throughput on Solid-State Memory-Based Mass Storage Device
Credit-Based Activity Regulation Within a Microprocessor Based on an Accumulative Credit System
Vector Mask Memory Access Instructions to Perform Individual and Sequential Memory Access Operations if an Exception Occurs During a Full Width Memory Access Operation
Methods and Apparatues for Wireless Network Communication Wherein a Universal Serial Bus Request Block (Urb) Is Generated That Will Vary Parameters That Controls Wireless Transmission Commands Between Devices
Detecting and indexing characters of videos by NCuts and page ranking
Phase Change Memory with Bipolar Junction Transistor Select Device
Transistor with Improved Tip Profile and Method of Manufacture Thereof
Metal Gate Transistors with Raised Source and Drain Regions Formed on Heavily Doped Substrate
Programming Bit Alterable Memories
Alert Management Messaging
Method and System for Improving the Quality of Deep Metadata Associated with Media Content
Bulk Non-Planar Transistor Having Strained Enhanced Mobility and Methods of Fabrication
Multi-Gate Device Having a T-Shaped Gate Structure
Method for Making a Semiconductor Device Having a High-K Gate Dielectric
Grouping Processors and Assigning Shared Memory Space to a Group in a Heterogeneous Computer Environment
Semiconductor Heterostructures to Reduce Short Channel Effects
Selectively Controlled Memory
Optimizing Performance and Power Consumption During Memory Power Down State
Supply Margining Method and Apparatus
Dual Staggered Vertically Polarized Variable Azimuth Beamwidth Antenna for Wireless Network
Lateral Undercut of Metal Gate in Soi Device
Interconnects Having Sealing Structures to Enable Selective Metal Capping Layers
Programming Multilevel Cell Phase Change Memories
Integrating Non-Peripheral Component Interconnect (Pci) Resources into a Personal Computer System
Method and Apparatus for Efficient Resource Utilization for Prescient Instruction Prefetch
Apparatus to Maximize Buffer Utilization in an I/O Controller
Transient Voltage Compensation System and Method
Low Noise Voltage Regulator
Memory Channel with Bit Lane Fail-Over
Method for Forming Self-Aligned Source and Drain Contacts Using a Selectively Passivated Metal Gate
Interconnect in Low-K Interlayer Dielectrics
Non-Blocking Uefi I/O Channel Enhancements
Dynamic Optimization for Removal of Strong Atomicity Barriers
Stress in Trigate Devices Using Complimentary Gate Fill Materials
Self-Aligned Insulating Etchstop Layer on a Metal Contact
Detecting Architectural Vulnerability of Processor Resources
Method of Manufacturing Semiconducting Device with Stacked Dice
Forward Feature Selection for Support Vector Machines
Metal Gate Structure and Method of Manufacturing Same
Method and Apparatus for Supporting Address Translation in a Virtual Machine Environment
Providing a Peripheral Component Interconnect (Pci)-Compatible Transaction Level Protocol for a System on a Chip (Soc)
Method for Making a Semiconductor Device Having a High-K Gate Dielectric Layer and a Metal Gate Electrode
Method and Apparatus to Adjust Voltage for Storage Location Reliability
Device, System, and Method of Scheduling Tasks of a Multithreaded Application
Thermal Sensor Device
Microelectronic Package with Self-Heating Interconnect
Winged Vias to Increase Overlay Margin
Advanced Multi-Channel Watermarking System and Method
Advanced Watermarking System and Method
System and Method for a Shared I/O Subsystem
L2 Tunneling-Based Low Latency Single Radio Handoffs
Buffering Techniques for Power Management
Techniques for Communications Based Power Management
Techniques for Communications Power Management Based on System States
Techniques for Collaborative Power Management for Heterogeneous Networks
Methods and Apparatus for Data Communication for Mobile Electronic Devices
Driver Transparent Message Signaled Interrupts
Multi-Die Integrated Circuit Device and Method
Migrating Execution of Thread Between Cores of Different Instruction Set Architecture in Multi-Core Processor and Transitioning Each Core to Respective on / Off Power State
Capillary Underfill of Stacked Wafers
Replacement Spacers for Mosfet Fringe Capacatance Reduction and Processes of Making Same
Programmable read only memory
Antenna training and tracking protocol
Low Power Termination for Memory Modules
Substrate Package with Through Holes for High Speed I/O Flex Cable
Component Reliability Budgeting System
Mimo Communication System and Method for Communicating with Single Antenna and Multi-Antenna Mobile Stations
Registers for Data Transfers
Application:
12/249,786 →
Publication:
US 2009/0119671
Nonplanar Semiconductor Device with Partially or Fully Wrapped Around Gate Electrode and Methods of Fabrication
Method and Apparatus of Daynamic Bandwidth Managment
Content Filtering for a Digital Audio Signal
Symbol De-Mapping Methods in Multiple-Input Multiple-Output Systems
Altering Operation of a Network Interface Controller Based on Network Traffic
Processor Power Consumption Control and Voltage Drop via Micro-Architectural Bandwidth Throttling
Methods for Multi-Band Wireless Communication and Bandwidth Management
Sequential Circuit with Error Detection
Circuts and Methods for Reducing Minimum Supply for Register File Cells
Directional Transmission Techniques
Dual Metal Interconnects for Improved Gap-Fill, Reliability, and Reduced Capacitance
Extended Thermal Management
Dynamic Cta Adjustment Across Superframes in a Wireless Network
Methods of forming low interface resistance rare earth metal contacts and structures formed thereby
Platform and Processor Power Management
Arrangements for Beam Refinement in a Wireless Network
Method of Forming Programmable Anti-Fuse Element
Processor Power Management Associated with Workloads
Pseudo Dual-Port Sram and a Shared Memory Switch Using Multiple Memory Banks and a Sideband Memory
Pre-Boot Recovery of a Locked Computer System
Filter for Network Intrusion and Virus Detection
Tessellator Whose Tessellation Time Grows Linearly with the Amount of Tessellation
Application:
12/347,114 →
Publication:
US 2010/0164954
High Speed Voltage Regulator with Integrated Loseless Current Sensing
State History Storage for Synchronizing Redundant Processors
Power Delivery System in Which Vrm and Cpu Exchange Power Consumption Measurements
Configurable Write Policy in a Memory System
Method and Apparatus for Selective Dram Precharge
Method of Forming a Nonplanar Transistor with Sidewall Spacers
Application:
12/369,642 →
Publication:
US 2009/0149012
Biometric Identification Data Protection
Application:
12/372,193 →
Publication:
US 2010/0208950
Distribution of tasks among asymmetric processing elements
Spectral shaping for multiband OFDM transmitters with time spreading
Application:
12/380,405 →
Publication:
US 2009/0252241
Mobile systems with seamless transition by activating second subsystem to continue operation of application executed by first subsystem as it enters sleep mode
Method, System, and Apparatus for Dynamic Clock Adjustment
Device Power Management in a Wireless Network
Microprocessor Die with Integrated Voltage Regulation Control Circuit
Memory Power Delivery Noise Suppression
Image forming techniques
Method and System for Interactive Fitness Training Program
Switching Display Update Properties Upon Detecting a Power Management Event
Mobile Device and Geographic Information System Background and Summary of the Related Art
Network Storage Target Boot and Network Connectivity Through a Common Network Device
Method and Apparatus for Dynamic Bandwidth Management
System and Method for Execution of a Secured Environment Initialization Instruction
Peer-To-Peer Negotiation in a Wireless Network
Use of Delayed Clear-to-Send and Denial-to-Send in Directional Wireless Networks
Wireless Access Point with Digital Television Capabilities
Apparatus and Associated Methods to Perform Space-Frequency Interleaving in a Multicarrier Wireless Communication Channel
Semiconductor Device Structures and Methods of Forming Semiconductor Structures
Protocol to Implement Token Id Mechanism for Network Data Transfer
Patent:
7,903,660 →
Application:
12/470,411 →
Methods and Apparatus for Integrity Measurement of Virtual Machine Monitor and Operating System via Secure Launch
Method and System to Facilitate Configurable Input/Output (I/O) Termination Voltage Reference
Dynamically Re-Classifying Data in a Shared Cache
Interconnecting Network Processors with Heterogeneous Fabrics
Localized Spacer For A Multi-Gate Transistor
Low-Power Subsystem for Portable Computers
Dynamic Power Control for Reduced Voltage Level of Graphics Controller Component of Memory Controller Based on Its Degree of Idleness
Embedding Device in Substrate Cavity
Transistor Gate Electrode Having Conductor Material Layer
Method and System for the Protected Storage of Downloaded Media Content via a Virtualized Platform
Method and Apparatus for Remotely Provisioning Software-Based Security Coprocessors
Methods and Systems to Estimate Motion Based on Reconstructed Reference Frames at a Video Decoder
Methods and Systems for Motion Vector Derivation at a Video Decoder
Mechanism to Flexibly Support Multiple Device Numbers on Point-to-Point Interconnect Upstream Ports
Increasing Memory Bandwidth in Processor-Based Systems
Managing and Implementing Metadata in Central Processing Unit Using Register Extensions
Remote Audio
Multi-Pattern Packet Content Inspection Mechanisms Employing Tagged Values
Methods and Apparatus for Adaptively Choosing a Search Range for Motion Estimation
Low speed access to dram
Performance enhancement of address translation using translation tables covering large address spaces
Application:
12/584,138 →
Publication:
US 2010/0011187
Filling the Space-Time Channels in Sdma
Filling the space-time channels in SDMA
Application:
12/584,780 →
Publication:
US 2010/0002677
Traffic Constraints in a Mmwave Wireless Network
Passive thermal solution for hand-held devices
Application:
12/586,065 →
Publication:
US 2010/0008047
Thermally and Electrically Conductive Structure Comprising a Carbon Nanotube and a Carbon Coating, and Method of Reducing a Contact Resistance of Same
Hardware Support for Thread Scheduling on Multi-Core Processors
Double-Pulse Write for Phase Change Memory
Radio-Frequency Reconfigurations of Microelectronic Systems in Commercial Packages
Method, System, and Apparatus for Dynamically Distributing a Computational Load Between Clusters of Cores at a Frequency Greater Than a Thermal Time Constant
Ofdm Receiver and Methods for Operating in High-Throughput and Increased Range Modes
Frame Rate Conversion Using Motion Estimation and Compensation
Method and Apparatus for Loading a Trustable Operating System
Method and Apparatus for Loading a Trustable Operating System
System and Method for Allocating and Deallocating Memory Within Transactional Code
Communication Subsystem for Wireless Devices or the Like
Fingerprinting Digital Video for Rights Management in Networks
Bss/Pbss Support and Schedule-Free Networking in 60GHZ
Dielectric Spacers for Metal Interconnects and Method to Form the Same
Apparatuses to Provide a Message Signaled Interrupt to Generate a Pci Express Interrupt
Amorphous Semiconductor Threshold Switch Volatile Memory Cell
Method and Apparatus for Dynamically Adjusting Voltage Reference to Optimize an I/O System
Antifuse Programmable Memory Array
Device, System and Method of Scheduling Communications with a Group of Wireless Communication Units
Application:
12/640,027 →
Publication:
US 2011/0149731
Communication Subsystem for Wireless Devices or the Like
Spin Torque Magnetic Integrated Circuits and Devices Therefor
Method and Apparatus for Connecting Packet Telephony Calls Between Secure and Non-Secure Networks
Image Buffering Techniques
Through Mold via Polymer Block Package
Method and System for Multiband Rate Scaling
Posting Interrupts to Virtual Processors
System and Method for Controlling Home Network Devices Using Multicast Enabled Remote Controls
System and Method for Controlling Home Network Devices Using Multicast Enabled Remote Controls
System and Method for Controlling Home Network Devices Using Multicast Enabled Remote Controls
Remote Audio
Robust Memory Link Testing Using Memory Controller
Tamper Resistant Fuse Design
Energy-Efficient Set Write of Phase Change Memory with Switch
Instruction-Set Architecture for Programmable Cyclic Redundancy Check (Crc) Computations
Adaptive Digital Phase Locked Loop
Direct Memory Access (Dma) Address Translation Between Peer Input/Output (I/O) Devices
Domain Name System Lookup Latency Reduction
Dma (Direct Memory Access) Coalescing
Recessed and Embedded Die Coreless Package
Germanium-Based Quantum Well Devices
Transition metal alloys for use as a gate electrode and devices incorporating these alloys
Application:
12/658,670 →
Publication:
US 2011/0097858
Operating system independent agent
Application:
12/660,338 →
Publication:
US 2010/0223625
Carbon Nanotube Coated Capacitor Electrodes
Systems for Communicating Using Multiple Frequency Bands in a Wireless Network
Method and System for Data Management in a Video Decoder
Object Storage
Electronic Programming Guide With Selectable Categories
Application:
12/697,374 →
Publication:
US 2010/0138790
Power Control Unit with Digitally Supplied System Parameters
Apparatus and Method to Maximize Buffer Utilization in an I/O Controller
Component Reliability Budgeting System
Tunable Gate Electrode Work Function Material for Transistor Applications
Method and Apparatus for Powered Off Processor Core Mode
Method and System for Gesture Recognition
Method and System for the Distribution of Software Products
Methods and Apparatus for Providing a Handover Control System Associated with a Wireless Communication Network
Load Adaptive Power Delivery
Share Resources and Increase Reliability in a Server Environment
Forming Abrupt Source Drain Metal Gate Transistors
Balancing Power Supply and Demand
Grid Array Connection Device and Method
Wireless Communication Device Integrated into a Single Package
Interworking of Networks with Single Radio Handover
Power Management System for Selectively Changing the Power State of Devices Using an Os Power Management Framework and Non-Os Power Management Framework
Three-Stage Architecture for Adaptive Clock Recovery
Performance and Traffic Aware Heterogeneous Interconnection Network
Interactive Delivery of Media Using Dynamic Playlist Generation Subject to Restrictive Criteria
Application:
12/749,177 →
Publication:
US 2010/0241701
Fast Exit from Self-Refresh State of a Memory Device
Payment Management on Mobile Devices
Forming in-Situ Micro-Feature Structures with Coreless Packages
Forming Metal Filled Die Back-Side Film for Electromagnetic Interference Shielding with Coreless Packages
Processor Control Register Virtualization to Minimize Virtual Machine Exits
Automated Process and Apparatus for Providing Integrated Management and Control of Computer Networks
Forming Functionalized Carrier Structures with Coreless Packages
Method and Apparatus for Forming Metal-Metal Oxide Etch Stop/Barrier for Integrated Circuit Interconnects
Methods and Systems to Read Register Files with Un-Clocked Read Wordlines and Clocked Bitlines, and to Pre-Charge a Bitline to a Configurable Voltage
Using Unstable Nitrides to Form Semiconductor Structures
Non-Volatile Storage for Graphics Hardware
Method for Selling Content Over a Network
Fabrication of Interconnects in a Low-K Interlayer Dielectrics
Method and System for Modeling Subjects from a Depth Map
Patent:
8,639,020 →
Application:
12/817,102 →
Group Ii Element Alloys for Protecting Metal Interconnects
Mold Compounds in Improved Embedded-Die Coreless Substrates, and Processes of Forming Same
Memory Write Operation Methods and Circuits
CLUSTERING MANAGEMENT IN mmWAVE WIRELESS SYSTEMS
System for Portable Tangible Interaction
Method and Apparatus for Reducing Power Consumption for Memories
User Interchangeable Ornamental Portions of Electronic Devices
Efficient Gesture Processing
Application:
12/835,079 →
Publication:
US 2012/0016641
Apparatus and Associated Methods to Perform Space-Frequency Interleaving in a Multicarrier Wireless Communication Channel
Memory Channel with Bit Lane Fail-Over
Providing Platform Independent Memory Logic
Integrating Non-Peripheral Component Interconnect (Pci) Resources into a Personal Computer System
Power Reducing Logic and Non-Destructive Latch Circuits and Applications
Apparatus and Method for a Thermal Management of a Memory Device
High-Voltage Transistor Architectures, Processes of Forming Same, and Systems Containing Same
Channel Access Mechanism for Wide Channels Used in Overlapping Networks
Shared-Memory Switch Fabric Architecture
Application:
12/862,539 →
Publication:
US 2010/0325370
Method and Apparatus for Using a Single Multi-Function Adapter with Different Operating Systems
Techniques for Primary Channel Selection for an 802.11AC Wireless Network Operating Adajacent to an 802.11N Wireless Network
Speculative Multi-Threading for Instruction Prefetch and/or Trace Pre-Build
Forming Inductor and Transformer Structures with Magnetic Materials Using Damascene Processing for Integrated Circuits
Method and System for Handling a Management Interrupt Event in a Multi-Processor Computing Device
Codec Control
Power Supply
Cluster Computing - Nic Based Os Provision
System and Method for 3D Video Stabilization by Fusing Orientation Sensor Readings and Image Alignment Estimates
Method for Enforcing Resource Access Control in Computer Systems
Methods of Forming Fully Embedded Bumpless Build-Up Layer Packages and Structures Formed Thereby
Reduced Current Requirements for Dram Self-Refresh Modes via Staggered Refresh Operations of Subsets of Memory Banks or Rows
Techniques to Transmit Commands to a Target Device to Reduce Power Consumption
Barrier Layers
Multiply Add Functional Unit Capable of Executing Scale, Round, Getexp, Round, Getmant, Reduce, Range and Class Instructions
Method, Apparatus and System to Determine Access Information for a Phase Change Memory
Allocation and Write Policy for a Glueless Area-Efficient Directory Cache for Hotly Contested Cache Lines
Application Scheduling in Heterogeneous Multiprocessor Computing Platform Based on a Ratio of Predicted Performance of Processor Cores
Nonplanar Semiconductor Device with Partially or Fully Wrapped Around Gate Electrode and Methods of Fabrication
Transistor Gate Electrode Having Conductor Material Layer
Transducer Access Point
Application:
12/895,460 →
Publication:
US 2011/0022194
Flex Cable and Method for Making the Same
Strain-Inducing Semiconductor Regions
Methods and Apparatuses for Idle-Prioritized Memory Ranks
Self-Aligned Selective Metal Contact to Source/Drain Diffusion Region
Hierarchical Dram Sensing
Patent:
8,406,073 →
Application:
12/928,948 →
Memory Module Thermal Management
Transaction Based Shared Data Operations in a Multiprocessor Environment
Providing a Peripheral Component Interconnect (Pci)-Compatible Transaction Level Protocol for a System on a Chip (Soc)
Methods for Forming Planarized Hermetic Barrier Layers and Structures Formed Thereby
Patent:
8,039,920 →
Application:
12/948,410 →
Method for Fabricating Transistor with Thinned Channel
Content Filtering for a Digital Audio Signal
Methods for Making Multi-Chip Packaging Using an Interposer
Reversible Low-Energy Data Storage in Phase Change Memory
Self-Aligned Insulating Etchstop Layer on a Metal Contact
Bumpless Build-Up Layer and Laminated Core Hybrid Structures and Methods of Assembling Same
Adaptive Wordline Programming Bias of a Phase Change Memory
Metal Gate Structure and Method of Manufacturing Same
Capacitor, Method of Increasing a Capacitance Area of Same, and System Containing Same
Dual Metal Interconnects for Improved Gap-Fill, Reliability, and Reduced Capacitance
Application:
12/967,865 →
Publication:
US 2011/0079910
Mobile Device and Geographic Information System Background and Summary of the Related Art
Millimeter-Wave Communication Station and Methods for Station and Information Discovery in a Millimeter-Wave Basic Service Set
Application:
12/969,954 →
Publication:
US 2012/0155443
Primitives to Enhance Thread-Level Speculation
Application:
12/970,040 →
Publication:
US 2011/0087867
Lower IC Package Structure for Coupling with an Upper IC Package to Form a Package-On-Package (PoP) Assembly and PoP Assembly Including Such a Lower IC Package Structure
Application:
12/970,114 →
Publication:
US 2012/0159118
Vertical Handover Composite Quality Measures
Audio Content Protection
Power Delivery Noise Reduction on a Memory Channel
Method and Apparatus for User-Activity-Based Dynamic Power Management and Policy Creation for Mobile Platforms
Designs and Methods for Conductive Bumps
Liner Layers for Metal Interconnects
Identifying and Accessing Individual Memory Devices in a Memory Channel
Providing Information Services Related to Multimodal Inputs
Providing Search Results from Visual Imagery
Application:
12/976,705 →
Publication:
US 2011/0092251
Disabling Outbound Drivers for a Last Memory Buffer on a Memory Channel
Lithography Mask Having Sub-Resolution Phased Assist Features
Multi-Gate Transistors
Digital Phase Lock Loop
Novel Fuse Programming Schemes for Robust Yield
Techniques for Face Detection and Tracking
Method, Apparatus and System for Selecting Wireless Network Controller
Method, Apparatus and System for Scheduling in a Wireless Communication Network
Method of Making Substrate Package with Through Holes for High Speed I/O Flex Cable
Memory Including Bipolar Junction Transistor Select Devices
Method and System for the Protected Storage of Downloaded Media Content via a Virtualized Platform
Microprocessor Die with Integrated Voltage Regulation Control Circuit
Cmos Devices with a Single Work Function Gate Electrode and Method of Fabrication
Semiconductor Structure Having a Capacitor and Metal Wiring Integrated in a Same Dielectric Layer
Application:
13/041,170 →
Publication:
US 2012/0223413
Dynamically Configuring a Video Decoder Cache for Motion Compensation
Forming a Non-Planar Transistor Having a Quantum Well Channel
System and Method for Allocating and Deallocating Memory Within Transactional Code
System and Method for Uninterrupted Streaming
Single Transistor Driver for Address Lines in a Phase Change Memory and Switch (Pcms) Array
Method and Apparatus to Reset a Phase Change Memory and Switch (Pcms) Memory Cell
Predefined Roaming and Idle Channels
Method and Apparatus for Wireless Network Communication Wherein a Universal Serial Bus Request Block (Urb) Is Generated That Will Vary Parameters That Controls Wireless Transmission Commands Between Devices
Dielectric Spacers for Metal Interconnects and Method to Form the Same
Multiple Write During Simultaneous Memory Access of a Multi-Port Memory Device
Grid Array Connection Device and Method
System, Method and Computer Program Product for Document Image Analysis Using Feature Extraction Functions
Enhancing Ps-Poll for Low-Power Wifi
Continued Virtual Links Between Gestures and User Interface Elements
Method, Apparatus and System for Providing Memory Sparing Information
Real-Time Depth Extraction Using Stereo Correspondence
Energy Efficient Power Distribution for 3D Integrated Circuit Stack
Method and Apparatus for Managing Charging Current
Techniques to Determine User Presence
System and Method for Creating and Displaying Classes of Graphical Display Objects
Self-Forming, Self-Aligned Barriers for Back-End Interconnects and Methods of Making Same
Transistor Gate Electrode Having Conductor Material Layer
Base Station and Method for Transmitting Downlink Reference Signals for Mimo Channel Estimation
Method and System for Reliable Multicast
Patent:
8,477,779 →
Application:
13/084,421 →
Simultaneous Multi-Voltage Rail Voltage Regulation Messages
Method of Embedding Passive Component Within Via
Low Power Termination for Memory Modules
Method and Apparatus for a Zero Voltage Processor Sleep State
Method, Apparatus, and System for Optimizing Frequency and Performance in a Multidie Microprocessor
Strain-Inducing Semiconductor Regions
Fast Verify for Phase Change Memory with Switch
Power Management Coordination in Multi-Core Processors
Drift Management in a Phase Change Memory and Switch (Pcms) Memory Device
Transaction Based Shared Data Operations in a Multiprocessor Environment
Power Reduction for System on Chip
Customized Travel Route System
Memory Module Bus Termination Voltage (Vtt) Regulation and Management
Circuits and Methods for Memory
Apparatus, System, and Method for Refreshing Non-volatile Memory
Stochastic Management of Power Consumption by Computer Systems
Mobile Augmented Reality System
Integrating Non-Peripheral Component Interconnect (Pci) Resources into a Personal Computer System
Method and System for Handling a Management Interrupt Event in a Multi-Processor Computing Device
Using Unstable Nitrides to Form Semiconductor Structures
Power Management of Electronic Devices Using Transitions Between Link States Based on Device Activity
Multi-Core Shared Page Miss Handler
Adaptive Wordline Programming Bias of a Phase Change Memory
System and Method for Aggregating Core-Cache Clusters in Order to Produce Multi-Core Processors
Predicting Future Power Level States For Processor Cores
Integrated Circuit and Process for Fabricating Thereof
Processor Power Consumption Control and Voltage Drop via Micro-Architectural Bandwidth Throttling
Application:
13/212,042 →
Publication:
US 2012/0210105
Method and Apparatus for Using a Single Multi-Function Adapter with Different Operating Systems
Vector Shuffle Instructions Operating on Multiple Lanes Each Having a Plurality of Data Elements Using a Same Set of Per-Lane Control Bits
Method and Apparatus for a Zero Voltage Processor Sleep State
Application:
13/220,413 →
Publication:
US 2012/0072750
Apparatus, System, and Method for Persistent User-Level Thread
Codec Control
Increasing Turbo Mode Residency Of A Processor
Dynamic Control of Reduced Voltage State of Graphics Controller Component of Memory Controller
Providing a Peripheral Component Interconnect (Pci)-Compatible Transaction Level Protocol for a System on a Chip (Soc)
Interconnects Having Sealing Structures to Enable Selective Metal Capping Layers
System and Method for Allocating Physical Random Access Channel Resources
Identifying and Accessing Individual Memory Devices in a Memory Channel
Method and Apparatus for Remotely Provisioning Software-Based Security Coprocessors
Variable Bandwidth Ofdm Receiver and Methods for Receiving Ofdm Signals of Different Bandwidths
Mechanism to Flexibly Support Multiple Device Numbers on Point-to-Point Interconnect Upstream Ports
Methods for Forming Planarized Hermetic Barrier Layers and Structures Formed Thereby
System and Method to Establish and Dynamically Control Energy Consumption in Large-Scale Datacenters or It Infrastructures
Semiconductor Device Structures and Methods of Forming Semiconductor Structures
Spin Torque Magnetic Integrated Circuits and Devices Therefor
Controlling Operating Frequency Of A Core Domain Via A Non-Core Domain Of A Multi-Domain Processor
Voltage regulation for a computer system providing voltage positioning for multi-component load
Providing a Sideband Message Interface for System on a Chip (Soc)
Primitives to Enhance Thread-Level Speculation
Techniques for Rapid Stereo Reconstruction from Images
Thermal Sensor Device
Optimizing Power Usage By Factoring Processor Architectural Events To PMU
Forward Feature Selection For Support Vector Machines
Virtual Links Between Different Displays to Present a Single Virtual Object
Multi-Protocol I/O Interconnect Architecture
Method, Apparatus, and System for Energy Efficiency and Energy Conservation Including Optimizing C-State Selection Under Variable Wakeup Rates
Interchangeable Connection Arrays for Double-Sided Dimm Placement
Stochastic Management of Power Consumption by Computer Systems
Patent:
8,296,591 →
Application:
13/340,394 →
Boundary Scan Chain for Stacked Memory
Disabling Outbound Drivers for a Last Memory Buffer on a Memory Channel
Split Deep Power Down of I/O Module
Techniques to Utilize Queues for Network Interface Devices
Circuits and Methods for Reducing Minimum Supply for Register File Cells
Arrangements for Beam Refinement in a Wireless Network
Radio Frequency Identification Tags Adapted for Localization and State Indication
Content Filtering for a Digital Audio Signal
Power-Scavenging Receiver to Generate a Signal to Be Used to Control Operational State
Reliability, Availability, and Serviceability Solution for Memory Technology
Pci Express Tunneling Over a Multi-Protocol I/O Interconnect
Method for Selling Content Over a Network
Method for Reducing Contact Resistance of a Thermally and Electrically Conductive Structure Comprising Carbon Nanotube
Single-Package Wireless Communication Device
Application:
13/371,663 →
Publication:
US 2012/0202436
Gesture Recognition Using Depth Images
Device Power Management in a Wireless Network
Systems and Methods for Accessing a Unified Translation Lookaside Buffer
Extended Thermal Management
Dynamic Optimization for Removal of Strong Atomicity Barriers
Application:
13/420,792 →
Publication:
US 2012/0174083
Techniques for Communications Power Management Based on System States
Application:
13/424,709 →
Publication:
US 2012/0178491
Method Of Correcting Adjacent Errors By Using BCH-Based Error Correction Coding
Systems for Communicating Using Multiple Frequency Bands in a Wireless Network
Memory Channel Having Deskew Separate from Redrive
Method and Apparatus for Cost and Power Efficient, Scalable Operating System Independent Services
Germanium-Based Quantum Well Devices
Reducing the memory requirements of a data switch
Application:
13/443,912 →
Publication:
US 2013/0100961
System and Method for Execution of a Secured Environment Initialization Instruction
Spin Torque Magnetic Integrated Circuits and Devices Therefor
Forming a Non-Planar Transistor Having a Quantum Well Channel
Tile-Level Snapback Detection Through Coupling Capacitor in a Cross Point Array
Power Reducing Logic and Non-Destructive Latch Circuits and Applications
Efficiency of Wireless Wide Area Networks Utilizing Local Wireless Connections
Apparatus and Associated Methods to Perform Space-Frequency Interleaving in a Multicarrier Wireless Communication Channel
Network Storage Target Boot and Network Connectivity Through a Common Network Device
Providing A Consolidated Sideband Communication Channel Between Devices
Patent:
8,549,205 →
Application:
13/477,304 →
Optimized Link Training and Management Mechanism
Patent:
8,437,343 →
Application:
13/477,310 →
Providing A Load/Store Communication Protocol With A Low Power Physical Unit
Patent:
8,446,903 →
Application:
13/477,322 →
Integrating Non-Peripheral Component Interconnect (PCI) Resources Into A Personal Computer System
Dynamically Configuring a Video Decoder Cache for Motion Compensation
Mimo Receiver and Method for Receiving Spatially-Multiplexed Ofdm Signals
Providing A Peripheral Component Interconnect (PCI)-Compatible Transaction Level Protocol For A System On A Chip (SoC)
Speed Up Secure Hash Algorithm (Sha) Using Single Instruction Multiple Data (Simd) Architectures
Speed Up Secure Hash Algorithm (Sha) Using Single Instruction Multiple Data (Simd) Architectures
Method, Apparatus and System of Dynamic Bandwidth Management
Method and Device for Securely Sharing Images Across Untrusted Channels
Method and Apparatus for Output of High-Bandwidth Debug Data/Traces in Ics and Socs Using Embedded High Speed Debug
Through Mold via Polymer Block Package
Codec Control
Authenticating A User Of A System Via An Authentication Image Mechanism
Charging a Battery Using a Multi-Rate Charge
Substrate Conductor Structure and Method
Advanced Watermarking System and Method
Controlling A Physical Link Of A First Protocol Using An Extended Capability Structure Of A Second Protocol
Multi-Mode Device (Mmd) Middleware for Cloud Spectrum Services Spectrum Allocation
Adaptive Wordline Programming Bias of a Phase Change Memory
Balancing Power Supply and Demand
No-Touch Stress Testing of Memory I/O Interfaces
Apparatus for Reducing Write Minimum Supply Voltage for Memory
Duty Cycle Compensation of Ram Transmitters
Flexible Command Addressing for Memory
Configuration for Power Reduction in Dram
Optimizing Energy Efficiency Using Device Idle Duration Information and Latency Tolerance Based on a Pre-Wake Configuration of a Platform Associated to the Device
Apparatus and Method for Selectively Using a Memory Command Clock as a Reference Clock
Bad Block Management Mechanism
Universal Charger
Compact Socket Connection to Cross-Point Array
Method and System for Perfect Shot Imaging from Multiple Images
Mobile Platform Software Update with Secure Authentication
Contact Resistance Reduced P-Mos Transistors Employing Ge-Rich Contact Layer
Mechanism for Facilitating Multiple Multimedia Viewing Planes in Media Display Systems
Low Power Universal Serial Bus
Remote Audio
Pixel-Adaptive Interpolation Algorithm for Image Upscaling
Adaptive Digital Phase Locked Loop
Simultaneous Multi-Voltage Rail Voltage Regulation Messages
Self-Aligned 3-D Epitaxial Structures for Mos Device Fabrication
Metallization of Fluorocarbon-Based Dielectric for Interconnects
Video Communication with Three Dimensional Perception
Media Workload Scheduler
Secure Data Protection with Improved Read-Only Memory Locking During System Pre-Boot
Hand Gesture Recognition System
Interconnecting Network Processors with Heterogeneous Fabrics
Method and Apparatus for Using a Single Multi-Function Adapter with Different Operating Systems
Semiconductor Device with Pre-Molding Chip Bonding
Off-Plane Conductive Line Interconnects in Microelectronic Devices
Automatic Media Distribution
Disabling Outbound Drivers for a Last Memory Buffer on a Memory Channel
Compressed Instruction Format
Optimizing Power Usage by Processor Cores Based on Architectural Events
Method and Apparatus to Process 4-Operand Simd Integer Multiply-Accumulate Instruction
Mechanism to Flexibly Support Multiple Device Numbers on Point-to-Point Interconnect Upstream Ports
Method and Apparatus for a Zero Voltage Processor Sleep State
Application:
13/619,998 →
Publication:
US 2013/0013945
Techniques and Apparatus for Audio Isolation in Video Processing
3D Memory Configurable for Performance and Power
Multiple Device Noise Reduction Microphone Array
Wireless Communication Station and Methods for Communicating Station-Capability Information
Techniques Associated with a Read and Write Window Budget for a Two Level Memory System
Techniques for Efficient Gpu Triangle List Adjacency Detection and Handling
Systems and Methods for Interference Mitigation in Heterogeneous Networks
Dynamic Control of Reduced Voltage State of Graphics Controller Component of Memory Controller
Non-Planar Semiconductor Device Having Group Iii-V Material Active Region with Multi-Dielectric Gate Stack
Methods of Forming Fully Embedded Bumpless Build-Up Layer Packages and Structures Formed Thereby
Associative Memory Oscillator Array
Methods of Providing Dielectric to Conductor Adhesion in Package Structures
Pitch Quartering to Create Pitch Halved Trenches and Pitch Halved Air Gaps
Forming Barrier Walls, Capping, or Alloys /Compounds Within Metal Lines
Decreased Switching Current in Spin-Transfer Torque Memory
System and Method for Performing Secure Communications
Instruction Set for Message Scheduling of SHA256 Algorithm
Providing Limited Access to a Service Device via an Intermediary
Methods of Containing Defects for Non-Silicon Device Engineering
Selectively Augmenting Communications Transmitted by a Communication Device
Method and Apparatus For Efficient Store/Restore of State Information During A Power State Transition
Land Side and Die Side Cavities to Reduce Package Z-Height
Bga Structure Using Ctf Balls in High Stress Regions
Active State Power Management (Aspm) to Reduce Power Consumption by Pci Express Components
Transaction-Level Testing of Memory I/O and Memory Device
Functional Memory Array Testing with a Transaction-Level Test Engine
Dynamically Switching A Workload Between Heterogeneous Cores Of A Processor
Parallelized Counter Tree Walk for Low Overhead Memory Replay Protection
Providing Information Services Related to Multimodal Inputs
Methods for Multi-Band Wireless Communication and Bandwidth Management
Patent:
8,982,820 →
Application:
13/651,739 →
Directional Transmission Techniques
Forming Metal Filled Die Back-Side Film for Electromagnetic Interference Shielding with Coreless Packages
Numa Aware Network Interface
Sequential Circuit with Error Detection
Detection of Return Oriented Programming Attacks
Dynamically Rebalancing Graphics Processor Resources
Primitives to Enhance Thread-Level Speculation
Application:
13/675,910 →
Publication:
US 2013/0073835
Augmenting Adas Features of a Vehicle with Image Processing Support in on-Board Vehicle Platform
Power-Efficient, Single-Ended Termination Using on-Die Voltage Supply
Network Storage Target Boot and Network Connectivity Through a Common Network Device
Method, System, and Apparatus for Dynamic Thermal Management
Network Storage Target Boot and Network Connectivity Through a Common Network Device
Method and Apparatus for User-Activity-Based Dynamic Power Management and Policy Creation for Mobile Platforms
Recording the Results of Visibility Tests at the Input Geometry Object Granularity
Gesture-Augmented Speech Recognition
Computing Platform Interface with Memory Management
Usb Device Interrupt Signal
Systems and Methods for Collecting Vehicle Evidence
Coexisting Standard and Proprietary Connection Usage
Disabling Outbound Drivers for a Last Memory Buffer on a Memory Channel
Semiconductor Interconnect Structures
Techniques for Enhancing Dielectric Breakdown Performance
Memory Subsystem Data Bus Stress Testing
Landside Stiffening Capacitors to Enable Ultrathin and Other Low-Z Products
Inductor Formed in Substrate
Method, Apparatus, And System For Optimizing Frequency And Performance In A Multidie Microprocessor
Techniques to Control Frame Display Rate
Gesture Pre-Processing of Video Stream to Reduce Platform Power
Bidirectional Power Management Techniques
Vertical Nanowire Transistor with Axially Engineered Semiconductor and Gate Metallization
Using Platform Idle Duration Information to Notify Platform Devices of Upcoming Active Periods
Reduction of Idle Power in a Communication Port
Epitaxial Film on Nanoscale Structure
High Density Interconnect Device and Method
Variable-Width Command/Address Bus
Defect Transferred and Lattice Mismatched Epitaxial Film
System and Method for Adaptive Skin Tone Detection
Power Management of Electronic Devices Utilizing Transitions Between Link States
Landing Structure for Through-Silicon Via
Detecting a User-to-Wireless Device Association in a Vehicle
Training for Command/Address/Control/Clock Delays Under Uncertain Initial Conditions and for Mapping Swizzled Data to Command/Address Signals
Memory Sense Amplifier Voltage Modulation
Discovery Mechanisms for Universal Serial Bus (Usb) Protocol Adaptation Layer
Switching Display Update Properties Upon Detecting a Power Management Event
Low Power Universal Serial Bus
Real Time Composition of a Composite Window from Content Maintaining Unique Security Domains
Instruction for Accelerating Snow 3G Wireless Security Algorithm
Instruction for Fast Zuc Algorithm Processing
Refresh Rate Performance Based on in-System Weak Bit Detection
Memory Subsystem Performance Based on in-System Weak Bit Detection
Frequency Selection Granularity for Integrated Circuits
Methods and Arrangements to Establish Peer-to-Peer Link
Methods and Arrangements for Beamforming Reports in Wireless Networks
Apparatus and Method for Reduced Core Entry into a Power State Having a Powered Down Core Cache
Modular Electronic Device System with a Detachable Display
Methods and Arrangements for Frequency Selective Transmission
Methods and Arrangements for Frequency Selective Transmission
Method to Integrate Arm Ecosystem Ips into Pci-Based Interconnect
Embedded Package in Pcb Build Up
Gesture Pre-Processing of Video Stream with Hold-Off Period to Reduce Platform Power
Creating a Sensory Experience in a Vehicle
Techniques for Use of Vendor Defined Messages to Execute a Command to Access a Storage Device
Techniques for Remote Client Access to a Storage Medium Coupled with a Server
Non-Cylindrical Conducting Shapes in Multilayer Laminated Substrate Cores
Microelectronic Package with Self-Heating Interconnect
Stress in Trigate Devices Using Complimentary Gate Fill Materials
Traffic Forwarding for Processing in Network Environment
Techniques for Enhancing Fracture Resistance of Interconnects
Device, System and Method of Scheduling Communications with a Group of Wireless Communication Units
Method and Apparatus of Multiband Communication
Optical Universal Serial Bus (Usb)
Assessment and Management of Emotional State of a Vehicle Operator
Memory Refresh Management
Increasing Turbo Mode Residency Of A Processor
Controlling Operating Frequency Of A Core Domain Based On Operating Condition Of A Non-Core Domain Of A Multi-Domain Processor
Fast Exit from Self-Refresh State of a Memory Device
Heat Removal in an Integrated Circuit Assembly Using a Jumping-Drops Vapor Chamber
Allocation and Write Policy for a Glueless Area-Efficient Directory Cache for Hotly Contested Cache Lines
Optimizing Power Usage by Factoring Processor Architectural Events to Pmu
Redundant Fuse Coding
Random Fuse Sensing
On-Die Programmable Fuses
Method, Apparatus, and System for Optimizing Frequency and Performance in a Multidie Microprocessor
Indicating Critical Battery Status in Mobile Devices
Instruction-Set Architecture for Programmable Cyclic Redundancy Check (Crc) Computations
Instructions and Logic to Perform Mask Load and Store Operations as Sequential or One-at-a-Time Operations After Exceptions and for Un-Cacheable Type Memory
Methods of Adding Dopants to Conductive Interconnect Structures in Substrate Technologies and Structures Formed Thereby
Apparatus, System and Method of Controlling Data Flow to a Plurality of Endpoints Over a Communication Network
Detection Of Return Oriented Programming Attacks
Gesture Pre-Processing of Video Stream Using a Markered Region
Gesture Pre-Processing of Video Stream Using Skintone Detection
Method for reducing power consumption in Solid-state storage device
Method, Apparatus, System for Qualifying Cpu Transactions with Security Attributes
Error and Erasure Decoding Apparatus and Method
Memory Receiver Circuit for Use with Memory of Different Characteristics
Adaptive Control Loop Protection for Fast and Robust Recovery from Low-Power States in High Speed Serial I/O Applications
Dynamically Calibrating Magnetic Sensors
APPARATUS, SYSTEM AND METHOD FOR A COMMON UNIFIED DEBUG ARCHITECTURE FOR INTEGRATED CIRCUITS AND SoCs
System and Method for Accessing Memory
System and Method for Execution of a Secured Environment Initialization Instruction
Posting Interrupts to Virtual Processors
Vector Shuffle Instructions Operating on Multiple Lanes Each Having a Plurality of Data Elements Using a Same Set of Per-Lane Control Bits
Sketch Aided Route Selection for Navigation Devices and Applications
Method, Apparatus, System, and Computer Readable Medium for Image Processing Software Module Configuration
Dual-Port Static Random Access Memory (Sram)
Method and System for Platform Management Messages Across Peripheral Component Interconnect Express (PCIE) Segments
Compare and Exchange Operation Using Sleep-Wakeup Mechanism
Instructions To Mark Beginning and End Of Non Transactional Code Region Requiring Write Back To Persistent Storage
Compressed Instruction Format
Device, System and Method for Communication with Heterogenous Physical Layers
Instruction Emulation Processors, Methods, and Systems
Key Refresh Between Trusted Units
Lithography Mask Having Sub-Resolution Phased Assist Features
Vehicular Occupancy Assessment
Providing a Peripheral Component Interconnect (Pci)-Compatible Transaction Level Protocol for a System on a Chip (Soc)
Forming in-Situ Micro-Feature Structures with Coreless Packages
Thermally and Electrically Conductive Structure Comprising a Carbon Nanotube, a Graphite Sheet and a Metal Layer; and Method of Reducing a Contact Resistance of Same
Hybrid Carbon-Metal Interconnect Structures
Optimized Link Training And Management Mechanism
Biometric Identification Data Protection
Application:
13/860,252 →
Publication:
US 2013/0230216
Mitigating Unauthorized Access to Data Traffic
Providing a Load/Store Communication Protocol with a Low Power Physical Unit
Package Substrate with High Density Interconnect Design to Capture Conductive Features on Embedded Die
Method and System for the Protected Storage of Downloaded Media Content via a Virtualized Platform
Interchangeable Connection Arrays for Double-Sided Dimm Placement
Techniques for Collaborative Power Management for Heterogeneous Networks
Patent:
45,600 →
Application:
13/889,472 →
Integrating Non-Peripheral Component Interconnect (PCI) Resources Into A Computer System
Self-Forming, Self-Aligned Barriers for Back-End Interconnects and Methods of Making Same
Application:
13/893,143 →
Publication:
US 2013/0260553
Multichip Integration with Through Silicon via (Tsv) Die Embedded in Package
Single Transistor Driver for Address Lines in a Phase Change Memory and Switch (Pcms) Array
Methods and Apparatus for Adaptively Choosing a Search Range for Motion Estimation
Passive Within Via
Circuits and Methods for Reducing Minimum Supply for Register File Cells
Controlling Power Delivery To A Processor Via A Bypass
Interface Engine Providing a Continuous User Interface
Application:
13/907,321 →
Method and System for Reliable Multicast
Method for Improving Bandwidth in Stacked Memory Devices
Apparatus, System, and Method for Persistent User-Level Thread
System and Method for the Distribution of Software Products
Codec Control
Method and System for Data Management in a Video Decoder
Application:
13/927,265 →
Publication:
US 2014/0010313
High-Voltage Transistor Architectures, Processes Of Forming Same, And Systems Containing Same
Package Assembly for Embedded Die and Associated Techniques and Configurations
Depth Camera System with Machine Learning for Recognition of Patches Within a Structured Light Pattern
Underfill Material Flow Control for Reduced Die-to-Die Spacing in Semiconductor Packages
Techniques, Apparatus, System and Method for Improved Display Calibration
Method of Creating a Maskless Air Gap in Back End Interconnects with Double Self-Aligned Vias
Techniques for Adaptive Demand/Response Energy Management of Electronic Systems
I/O Driver Transmit Swing Control
Bumpless Build-Up Layer and Laminated Core Hybrid Structures and Methods of Assembling Same
Dynamic Control of Reduced Voltage State of Graphics Controller Component of Memory Controller
Platform and Processor Power Management
Techniques for Touch and Non-Touch User Interaction Input
Systems and Methods for Migrating Processes Among Asymmetrical Processing Cores
Distribution of Tasks Among Asymmetric Processing Elements
Distribution of Tasks Among Asymmetric Processing Elements
User Interchangeable Ornamental Portions of Electronic Devices
Application:
13/957,917 →
Publication:
US 2013/0314862
Strain-Inducing Semiconductor Regions
Formation of Dram Capacitor Among Metal Interconnect
File Encryption, Decryption and Accessvia Near Field Communication
Charge-Saving Power-Gate Apparatus and Method
Secure Peer-to-Peer Network Setup
Power Efficient Level One Data Cache Access With Pre-Validated Tags
Bbul Material Integration in-Plane with Embedded Die for Warpage Control
Systems and Methods for Providing Anti-Malware Protection on Storage Devices
Low Power Transient Voltage Collapse Apparatus and Method for a Memory Cell
Memory Device Responding to Device Commands for Operational Controls
High Voltage Field Effect Transistors
Integrated Inductor for Integrated Circuit Devices
Collaborative Processor and System Performance and Power Management
Collaborative Processor and System Performance and Power Management
Technologies for Displaying Images During a Pre-Boot Phase of a Vehicle Computing Platform
Buffer-Related Usb Communication
Method and Apparatus for Atomic Frequency and Voltage Changes
Crosstalk Cancellation and/or Reduction
Adaptive Voltage Input to a Charge Pump
Apparatus and Method for Improving Power Delivery in a Memory, Such as, a Random Access Memory
Techniques for Improving Stereo Block Matching with the Pyramid Method
Process Tunable Resistor with User Selectable Values
Human Head Detection in Depth Images
A Method and Device to Augment Volatile Memory in a Graphics Subsystem with Non-Volatile Memory
System and Method for Avatar Creation and Synchronization
Content-Aware Image Resizing Using Superpixels
Service of an Emergency Event Based on Proximity
Runtime Dispatching Among a Heterogeneous Group of Processors
Strained Channel Region Transistors Employing Source and Drain Stressors and Systems Including the Same
Separate Microchannel Voltage Domains in Stacked Memory Architecture
Multi-Vehicle Surveillance System
Systems, Methods, and Apparatus for Controlling Devices Based on a Detected Gaze
Computing Performance and Power Management with Firmware Performance Data Structure
Collaborative Processor and System Performance and Power Management
Vehicular Speech Recognition Grammar Selection Based Upon Captured or Proximity Information
User-To-User Communication Enhancement with Augmented Reality
Navigation Systems and Associated Methods
Energy Storage Device, Method of Manufacturing Same, and Mobile Electronic Device Containing Same
Inter-View Filter Parameters Re-Use for Three Dimensional Video Coding
Systems, Methods, and Apparatus for Controlling Gesture Initiation and Termination
Object Recognition and Notification
Computing Platform Performance Management with Ras Services
Memory Channel That Supports Near Memory and Far Memory Access
Dynamic Interrupt Reconfiguration for Effective Power Management
System, Methods, and Apparatus for in-Vehicle Fiducial Mark Tracking and Interpretation
Systems, Methods, and Apparatus for Identifying an Occupant of a Vehicle
Computing Platform with Interface Based Error Injection
Computing Platform Interface with Memory Management
Etchstop Layers and Capacitors
High Density Package Interconnects
Methods and Apparatus for Saving Power
Determining Relative Positioning Information
Mechanism for Facilitating Power Extension Service at Computing Devices
Method and Apparatus for Face Detection in a Frame Sequence Using Sub-Tasks and Layers
Methods, Systems and Apparatuses to Mitigate Communication Collisions
Obtaining Vendor Information Using Mobile Internet Devices
Interlayer Dielectric for Non-Planar Transistors
Ultra-Capacitor Based Energy Storage in a Battery Form Factor
Automated Driver Alert System
Apparatus, Systems and Methods for Wireless Charging for Pc Platforms and Peripherals
Multiband Central Controller and Method for Multiband Network Operations
Privacy-Enhanced Car Data Distribution
User Equipment and Method for Pico-Cell Attachment and Attachment Inhibiting
Object of Interest Based Image Processing
Raw Memory Transaction Support
Migrating Tasks Between Asymmetric Computing Elements of a Multi-Core Processor
3D Interconnect Structure Comprising Through-Silicon Vias Combined with Fine Pitch Backside Metal Redistribution Lines Fabricated Using a Dual Damascene Type Approach
Logic Chip Including Embedded Magnetic Tunnel Junctions
Logic Chip Including Embedded Magnetic Tunnel Junctions
System and Method for Intelligently Flushing Data from a Processor into a Memory Subsystem
Isolating, at Least in Part, Local Row or Column Circuitry of Memory Cell Before Establishing Voltage Differential to Permit Reading of Cell
Server Including Switch Circuitry
Semiconductor Device with Isolated Body Portion
Semiconductor Device Having Metallic Source and Drain Regions
Bit Cell Write-Assistance
Incorporating Access Control Functionality into a System on a Chip (Soc)
Apparatus and Method for Sliding Window Data Access
Two-Level Optimization for Cloud Spectrum Services
Providing an Asymmetric Multicore Processor System Transparently to an Operating System
Implementing Cloud Spectrum Services Modes of Transaction
Application:
13/996,416 →
Publication:
US 2015/0296485
Spin Transfer Torque Memory (Sttm) Device with Half-Metal and Method to Write and Read the Device
Apparatus and Method for Vector Instructions for Large Integer Arithmetic
System and Method for Enhanced Dmvd Processing
High Stability Spintronic Memory
Multiple Radio Devices for Implementing Dynamic Band Access Background
Cloud Based Spectrum Management Analytics
Application:
13/997,010 →
Publication:
US 2014/0220999
Cross Point Array Mram Having Spin Hall Mtj Devices
Implementing Third Generation Partnership Project Protocols That Combine Use of International Mobile Telecommunication Bands and Non-International Mobile Telecommunication Bands of Licensed Wireless Communication Spectrum
Apparatus, System, and Method for Voltage Level Switching
Stacked Memory with Interface Providing Offset Interconnects
A Method of Forming a Semiconductor Device with Tall Fins and Using Hard Mask Etch Stops
Airgap Interconnect with Hood Layer and Method of Formiing
Apparatus and Method for Implementing a Multi-Level Memory Hierarchy
User Identification and Personalized Vehicle Settings Management System
Avatar Animation, Social Networking and Touch Screen Applications
System and Method for Avatar Management and Selection
Method of Detecting Facial Attributes
Balancing Energy Barrier Between States in Perpendicular Magnetic Tunnel Junctions
Providing Snoop Filtering Associated with a Data Buffer
Negative Bitline Write Assist Circuit and Method for Operating the Same
Generic Address Scrambler for Memory Circuit Test Engine
Method, System, and Device for Selecting and Displaying Information on a Mobile Digital Display Device
Device Resource Management Based on Contextual Planning
Supervisor Mode Execution Protection
Fabrication of Porous Silicon Electrochemical Capacitors
Contact Techniques and Configurations for Reducing Parasitic Resistance in Nanowire Transistors
Spin Transfer Torque Based Memory Elements for Programmable Device Arrays
Memory Operations Using System Thermal Sensor Data
Techniques for Command Validation for Access to a Storage Device by a Remote Client
Providing A Consolidated Sideband Communication Channel Between Devices
Solder Attach Apparatus and Method
Distribution of Tasks Among Asymmetric Processing Elements
Data Movement in Memory Devices
Timing Control for Unmatched Signal Receiver
Method and Apparatus for Remotely Provisioning Software-Based Security Coprocessors
Directed Per Bank Refresh Command
Interconnects with Fully Clad Lines
Method, System, and Apparatus for Dynamic Thermal Management
Bi-Directional Charger for Battery Device with Control Logic Based on Sensed Voltage and Device Type
Power Consumption Monitoring Device for a Power Source
Hybrid Phase Field Effect Transistor
Method, Apparatus, and System for Optimizing Frequency and Performance in a Multidie Microprocessor
Die Assembly on Thin Dielectric Sheet
Wireless Access Point with Digital Television Capabilities
Semiconductor Device Structures and Methods of Forming Semiconductor Structures
Generating Multiple Secure Hashes from a Single Data Buffer
Network Storage Target Boot and Network Connectivity Through a Common Network Device
3D Object Tracking
Germanium-Based Quantum Well Devices
Optical and Electrical Connector
Method and Apparatus for Dynamically Adjusting Voltage Reference to Optimize an I/O System
Bss/Pbss Support and Schedule-Free Networking in 60 Ghz
Backchannel Communications For Initialization of High-Speed Networks
Retractable Displays for Helmets
Compacted Context State Management
Forming Functionalized Carrier Structures with Coreless Packages
Supply Margining Method and Apparatus
Apparatus and Method for Thermal Management of a Memory Device
Data Prioritization, Storage and Protection in a Vehicular Communication System
Method for Training a Control Signal Based on a Strobe Signal in a Memory Module
Patent:
9,025,399 →
Application:
14/099,315 →
Coordinating Power Mode Switching and Refresh Operations in a Memory Device
Patent:
9,001,608 →
Application:
14/099,621 →
Techniques for Disparity Estimation Using Camera Arrays for High Dynamic Range Imaging
Efficient Facial Landmark Tracking Using Online Shape Regression Method
Techniques for Adding Interactive Features to Videos
Hybrid Threading
Optimized Link Training And Management Mechanism
Automated Privacy Adjustments to Video Conferencing Streams
Locality Adapted Computerized Assisted or Autonomous Driving of Vehicles
Signaling a Synchronization Frame Transmission Request
Tracking Mode of a Processing Device in Instruction Tracing Systems
Cancellation of Interfering Audio on a Mobile Device
Methods and Apparatus to Identify Privacy Relevant Correlations Between Data Values
Adaptive Interior Air Quality Control Apparatus and Methods for Vehicle Compartment
Configuring User Customizable Operational Features of a Vehicle
Apparatus for Low Power Write and Read Operations for Resistive Memory
Current-Mode Digital Temperature Sensor Apparatus
Apparatus, System and Method of Communicating Positioning Information
Method and Apparatus for Controlling Screen by Tracking Head of User Through Camera Module, and Computer-Readable Recording Medium Therefor
Digital Advertising System
Application:
14/129,344 →
Publication:
US 2014/0122248
Low Resistance Bitline and Sourceline Apparatus for Improving Read and Write Operations of a Nonvolatile Memory
Bandgap Reference Circuit with Low Output Impedance Stage and Power-on Detector
Presenting Advertisements During Media Content Seek
Sharing Embedded Hardware Resources
Techniques for Providing an Augmented Reality View
Controlling A Physical Link Of A First Protocol Using An Extended Capability Structure Of A Second Protocol
Low Speed Access to Dram
Reconfigurable Processing Unit
Strain-Inducing Semiconductor Regions
Additives to Improve the Performance of a Precursor Source for Cobalt Deposition
Traffic and/or Workload Processing
Method and System for Modeling Subjects from a Depth Map
Cobalt Based Interconnects and Methods of Fabrication Thereof
Dyanamically Adapting a Voltage of a Clock Generation Circuit
Method of Forming High Density, High Shorting Margin, and Low Capacitance Interconnects by Alternating Recessed Trenches
Apparatus, Method and System to Determine Memory Access Command Timing Based on Error Detection
Platform Power Consumption Reduction via Power State Switching
Techniques for Forming Interconnects in Porous Dielectric Materials
Method, Apparatus, and System for Optimizing Frequency and Performance in a Multidie Microprocessor
Method and Apparatus for Remotely Provisioning Software-Based Security Coprocessors
Determining A High Data Rate For Backchannel Communications For Initialization of High-Speed Networks
Apparatus for a Monotonic Delay Line, Method for Fast Locking of a Digital Dll with Clock Stop/Start Tolerance, Apparatus and Method for Robust Clock Edge Placement, and Apparatus and Method for Clock Offset Tuning
Processor With Transactional Capability and Logging Circuitry To Report Transactional Operations
SM3 Hash Function Message Expansion Processors, Methods, Systems, and Instructions
Systems and Methods for Automatic Root Port to Non-Transparent Bridge Switching for a Pci Express Interconnect Architecture
Boundary Scan Chain for Stacked Memory
User Interchangeable Ornamental Portions of Electronic Devices
Application:
14/145,767 →
Publication:
US 2014/0118913
User Interchangeable Ornamental Portions of Electronic Devices
Application:
14/145,772 →
Publication:
US 2014/0112652
Method and Apparatus for Dynamically Adjusting Voltage Reference to Optimize an I/O System
Distribution of Tasks Among Asymmetric Processing Elements
Systems and Methods for Selling Content Over a Network
System and Method for the Distribution of Software Products
Application:
14/163,758 →
Publication:
US 2014/0207625
Low Power Circuit for Transistor Electrical Overstress Protection in High Voltage Applications
Self-Aligned Insulating Etchstop Layer on a Metal Contact
Optimizing Power Usage by Factoring Processor Architectural Events to Pmu
Increasing Turbo Mode Residency of a Processor
Providing A Load/Store Communication Protocol With A Low Power Physical Unit
Vehicle Mirror Adjustment
Write Operations in Spin Transfer Torque Memory
Embedded Die Flip-Chip Package Assembly
Integrated Circuit Package
Efficient Gesture Processing
Method and Apparatus for Proactive Throttling for Improved Power Transitions in a Processor Core
Multiport Memory Cell Having Improved Density Area
Filling the Space-Time Channels in Sdma
System and Method for Execution of a Secured Environment Initialization Instruction
Orchestrating Autonomous Movements of Parked Vehicles to Optimize Parking Efficiency
Systems and Methods for Reducing Power Consumption
Method, Apparatus and System for Determining a Write Recovery Time of a Memory Based on Temperature
Space Transformer
On Demand Customization of Mobile Computing Devices
Determination of Mobile Display Position and Orientation Using Micropower Impulse Radar
Alternate Dynamic Keyboard for Convertible Tablet Computers
Radar-Based Gesture Recognition
Laser Cavity Formation for Embedded Dies or Components in Substrate Build-Up Layers
Inferred Undocking for Hybrid Tablet Computer
Virtual Links Between Different Displays to Present a Single Virtual Object
Technologies for Skipping Through Media Content
Instruction-Set Architecture for Programmable Cyclic Redundancy Check (Crc) Computations
Method And Apparatus For A Zero Voltage Processor
Method And Apparatus For A Zero Voltage Processor Sleep State
Recessed and Embedded Die Coreless Package
Power Management of Low Power Link States
Structured Stereo
Controls and Indicators with on-Screen Cognitive Aids
System, Apparatus And Method For Integrating Non-Peripheral Component Interconnect (PCI) Resources Into A Personal Computer System
Providing A Peripheral Component Interconnect (PCI)-Compatible Transaction Level Protocol For A System On A Chip (SoC)
Methods of Containing Defects for Non-Silicon Device Engineering
Automatic White Balancing with Chromaticity Measure of Raw Image Data
Assist Circuits for Sram Testing
Gesture Recognition Using Depth Images
Application:
14/271,191 →
Publication:
US 2014/0300539
Stress in Trigate Devices Using Complimentary Gate Fill Materials
Battery Charger for Different Power Sources
Power Delivery System
Gesture Pre-Processing of Video Stream Using a Markered Region
Mobile Systems with Seamless Transition by Activating Second Subsystem to Continue Operation of Application Executed by First Subsystem as It Enters Sleep Mode
Forming in-Situ Micro-Feature Structures with Coreless Packages
Self-Aligning a Processor Duty Cycle with Interrupts
Pci Express Tunneling Over a Multi-Protocol I/O Interconnect
Method For Enforcing Resource Access Control In Computer Systems
Memory Channel Having Deskew Separate from Redrive
Codec Control
Compressed Instruction Format
Techniques for Generating a Routing Table for a Mesh Network Having Ad Hoc Connections
Application:
14/314,955 →
Publication:
US 2015/0382278
Eye Display Interface for a Touch Display Device
Power Optimization with Dynamic Frame Rate Support
Method, Apparatus, and System for Energy Efficiency and Energy Conservation Including Optimizing C-State Selection Under Variable Wakeup Rates
Method of Submitting Graphics Workloads and Handling Dropped Workloads
Systems and Methods for Interference Mitigation in Heterogeneous Networks
Method and Apparatus for Bluetooth-Based General Service Discovery
Dynamically Applying Refresh Overcharge Voltage to Extend Refresh Cycle Time
Resistive Memory Write Operation with Merged Reset
Semiconductor Interconnect Structures
Adaptive Learning Environment Driven by Real-Time Identification of Engagement Level
Apparatuses and Methods for Reducing Switching Jitter
Configuration for Power Reduction in Dram
Ultra Low Power Architecture to Support Always on Path to Memory
Mid-Thread Pre-Emption with Software Assisted Context Switch
Non-Planar Semiconductor Device Having Active Region with Multi-Dielectric Gate Stack
Method and Device for Processing Digital Image, and Computer-Readable Recording Medium for Processing Digital Image
Method and System for Cache Tiering
Methods and Systems to Selectively Boost an Operating Voltage of, and Controls to an 8T Bit-Cell Array and/or Other Logic Blocks
Methods and Systems to Read a Magnetic Tunnel Junction (Mtj) Based Memory Cell Based on a Pulsed Read Current
Adaptive Zone of Safety
Aggregated Analytics for Intelligent Transportation Systems
Mechanism for Facilitaing Dynamic Simulation of Avatars Corresponding to Changing User Performances as Detected at Computing Devices
Individual Driving Preference Adapted Computerized Assist or Autonomous Driving of Vehicles
Bowl-Shaped Imaging System
Technologies for Providing Information to a User While Traveling
Integrated Circuit Package Substrate
Techniques for Processing Subtitles
Controlling a Camera with Face Detection
Location-Based Assistance for Personal Planning
Systems and Techniques for User Interface Control
Decreased Switching Current in Spin-Transfer Torque Memory
Audio Signal Beam Forming
Apparatus, Method and System for Determining Reference Voltages for a Memory
Transducer Access Point
Application:
14/455,081 →
Publication:
US 2014/0350697
Systems and Methods for Transmitting and Managing Communication on Dedicated Short-Range Communication Channels
Embedded Universal Serial Bus Solutions
Controlling Temperature Of A System Memory
Voltage Regulation for a Computer System
Dual Side Solder Resist Layers for Coreless Packages and Packages with an Embedded Interconnect Bridge and Their Methods of Fabrication
Posting Interrupts to Virtual Processors
Advanced Watermarking System and Method
Enhancing Ps-Poll for Low-Power Wifi
Technologies for Communicating Roadway Information
Jurisdiction-Based Adaptive Communication Systems and Methods
Technologies for Adjusting a Perspective of a Captured Image for Display
Object Visualization in Bowl-Shaped Imaging Systems
Systems and Methods for Rate Adaptation in Full-Duplex Wireless Communication
Apparatus, System and Method for Determining Comparison Information Based on Memory Data
Semiconductor Device with Pre-Molding Chip Bonding
Video Quality Enhancement
Methods and Systems for Optimizing Location-Based Wireless Charging
Controlling Power in a Multi-Port Usb Power Delivery System
System and Method for Electronically Tagging Items for Use in Controlling Electrical Devices
Method And Apparatus For A Zero Voltage Processor
Method and Apparatus for a Zero Voltage Processor
Techniques for Power Supply Topologies with Capacitance Management to Reduce Power Loss Associated with Charging and Discharging When Cycling Between Power States
Systems, Methods, and Devices for Social Proximity Fine Timing Measurement Requests Multicast Signaling
Wearable Sensor Data to Improve Map and Navigation Data
Adapting Operating Parameters of an Input/Output (Io) Interface Circuit of a Processor
Providing A Sideband Message Interface For System On A Chip (SoC)
Dynamic Control of Reduced Voltage State of Graphics Controller Component of Memory Controller
Serial Bus Electrical Termination Control
Distribution of Tasks Among Asymmetric Processing Elements
Distribution of Tasks Among Asymmetric Processing Elements
Technologies for Reporting and Predicting Emergency Vehicle Routes
Distribution of Tasks Among Asymmetric Processing Elements
Shoe-Based Wearable Interaction System
Camera Calibration
Hardware Apparatuses and Methods to Control Access to a Multiple Bank Data Cache
Magnetic Field-Assisted Memory Operation
Content Adaptive Telecine and Interlace Reverser
Device, System and Method of Scheduling Communications with a Group of Wireless Communication Units
Balancing Power Supply and Demand
High Density Interconnect Device and Method
Application:
14/518,421 →
Publication:
US 2015/0035144
Platform and Processor Power Management
Mechanism for Facilitating Multiple Multimedia Viewing Planes in Media Display Systems
Vertical Nanowire Transistor with Axially Engineered Semiconductor and Gate Metallization
Information Services for Real World Augmentation
Application:
14/538,544 →
Publication:
US 2015/0067041
Method and Apparatus for Atomic Frequency and Voltage Changes
L2 Tunneling Based Low Latency Single Radio Handoffs
Application:
14/540,579 →
Publication:
US 2015/0071251
Clustering Management in Mmwave Wireless Systems
Dynamically Associated Neighbor Awareness Networking (Nan) Discovery Windows for Fine Timing Measurement
Non-Volatile Register File Including Memory Cells Having Conductive Oxide Memory Element
Apparatus and Method to Provide Multiple Domain Clock Frequencies In A Processor
Voltage Level Shifter Circuit
Providing A Consolidated Sideband Communication Channel Between Devices
Forming A Non-Planar Transistor Having A Quantum Well Channel
Multiply Add Functional Unit Capable of Executing Scale, Round, Getexp, Round, Getmant, Reduce, Range and Class Instructions
Biasing Scheme for High Voltage Circuits Using Low Voltage Devices
Multiple User Biometric for Authentication to Secured Resources
Landing Structure for Through-Silicon Via
Application:
14/563,926 →
Publication:
US 2015/0137368
Disparity Search Range Determination for Images from an Image Sensor Array
Protecting Privacy with Secure Digital Signage in Vehicle Registration Plates
A Circuit Board Having a Signal Layer with Signal Traces and a Reference Plane with an Additional Signal Trace Larger Than the Signal Traces
Interconnects Having Sealing Structures to Enable Selective Metal Capping Layers
Apparatus, System and Method for Caching Compressed Data
Mechanism for Extending Cycle Life of a Battery
Apparatuses, Methods, and Systems for Dense Circuitry Using Tunnel Field Effect Transistors
Semiconductor Device Structures and Methods of Forming Semiconductor Structures
Digital Phase Controlled Delay Circuit
Bi-Directional Community Information Brokerage
Methods and Systems to Estimate Motion Based on Reconstructed Reference Frames at a Video Decoder
Techniques to Transmit Commands to a Target Device
Application:
14/578,999 →
Publication:
US 2015/0113308
Multiple write during simultaneous memory access of a multi-port memory device
Patent:
46,474 →
Application:
14/579,337 →
System and Method for Interacting with Digital Signage
Write Operations in Spin Transfer Torque Memory
Adaptive Charge Current for a Battery
Techniques to Reduce Memory Cell Refreshes for a Memory Device
Location Grouping
Patent:
9,351,122 →
Application:
14/581,790 →
Method and Apparatus for Energy Harvest from a Proximity Coupling Device
ASSISTANCE INFORMATION FOR EVOLVED NODE B (eNB) PARAMETER TUNING
Polarity Based Data Transfer Function for Volatile Memory
Type-C Retimer State Machine and a Protocol for Inband Control and Configuration
System and Method for Joining Neighbor Awareness Networking Hidden Clusters
Apparatus, System and Method of Communicating Traffic to a Plurality of Peer to Peer Devices
Control of Power Consumption
Techniques for Mmwave-Capable Small Cell Detection
Circuits for Digital and Analog Controlled Oscillators
Stacked Memory with Interface Providing Offset Interconnects
Mobile Device and Geographic Information System Background and Summary of the Related Art
Systems and Methods for Accessing a Unified Translation Lookaside Buffer
Personal Communication Drone
Optimizing Power Usage by Factoring Processor Architectural Events to Pmu
Method and Apparatus for Remotely Provisioning Software-Based Security Coprocessors
Bidirectional Power Management Techniques
Method and System for the Protected Storage of Downloaded Media Content via a Virtualized Platform
Performing Power Management in a Multicore Processor
Forming Functionalized Carrier Structures with Coreless Packages
Authenticating a User of a System via an Authentication Image Mechanism
Method of Creating a Maskless Air Gap in Back End Interconnections with Double Self-Aligned Vias
Method And Apparatus For A Zero Voltage Processor Sleep State
Multichip Integration with Through Silicon via (Tsv) Die Embedded in Package
Technologies for Fast Low-Power Startup of a Computing Device
Apparatus to Reduce Retention Failure in Complementary Resistive Memory
Patent:
9,373,395 →
Application:
14/638,942 →
Method for Training a Control Signal Based on a Strobe Signal in a Memory Module
Grid Array Connection Device and Method
Non-Local Means Image Denoising with an Adaptive Directional Spatial Filter
Changing Cache Ownership in Clustered Multiprocessor
Apparatus and Method for Page Copying Within Sections of a Memory
Self-Storing and Self-Restoring Non-Volatile Static Random Access Memory
Selectively Enabling First and Second Communication Paths Using a Repeater
Method and Apparatus for Remotely Provisioning Software-Based Security Coprocessors
Virtual Intelligent Platform Management Interface (Ipmi) Satellite Controller and Method
Additional Secured Execution Environment with Sr-Iov and Xhci-Iov
Technologies for Assisting Vehicles with Changing Road Conditions
High-Voltage Transistor Architectures, Processes of Forming Same, and Systems Containing Same
Non-Planar Semiconductor Device Having Group Iii-V Material Active Region with Multi-Dielectric Gate Stack
Navigation Systems and Associated Methods
Antenna Training and Tracking Protocol
Bitcell State Retention
Nanoscale Structure with Epitaxial Film Having a Recessed Bottom Portion
Method, Apparatus and System for Modular on-Die Coherent Interconnect for Packetized Communication
Method of Forming High Density, High Shorting Margin, and Low Capacitance Interconnects by Alternating Recessed Trenches
Head Pose Determination Using a Camera and a Distance Determination
Conductive Paths Through Dielectric with a High Aspect Ratio for Semiconductor Devices
Semiconductor Structure Having a Capacitor and Metal Wiring Integrated in a Same Dielectric Layer
Programmable Memory Device Sense Amplifier
Patent:
9,478,308 →
Application:
14/721,854 →
Non-Volatile Storage for Graphics Hardware
Method and Apparatus for Remotely Provisioning Software-Based Security Coprocessors
Method and Apparatus for Remotely Provisioning Software-Based Security Coprocessors
Method and Apparatus for Remotely Provisioning Software-Based Security Coprocessors
Fin Structure having Hard Mask Etch Stop Layers underneath Gate Sidewall Spacers
Discovery Mechanisms for Universal Serial Bus (Usb) Protocol Adaptation Layer
Read and Write Apparatus and Method for a Dual Port Memory
Metallization of Fluorocarbon-Based Dielectric for Interconnects
Techniques for Rapid Stereo Reconstruction from Images
Etchstop Layers and Capacitors
Methods of Containing Defects for Non-Silicon Device Engineering
User Interaction with Wearable Devices
Methods and Systems for Motion Vector Derivation at a Video Decoder
Facilitating Environment-Based Lossy Compression of Data for Efficient Rendering of Contents at Computing Devices
Patent:
9,491,490 →
Application:
14/738,642 →
Techniques for Efficient Gpu Triangle List Adjacency Detection and Handling
Systems for Communicating Using Multiple Frequency Bands in a Wireless Network
Semiconductor Interconnect Structures
Secure Protection Block and Function Block System and Method
Apparatuses and Systems for Increasing a Speed of Removal of Data Stored in a Memory Cell
Apparatus, System and Method of Neighbor Awareness Networking (Nan) Geo-Fencing
Latched Comparator Circuit
Apparatus, System and Method of Dynamic Allocation Using a Grant Frame
Simulating Multi-Camera Imaging Systems
Alerting on Proximity of Items
Wearable Device with Gesture Recognition Mechanism
Digitally Trimmable Integrated Resistors Including Resistive Memory Elements
Array Imaging System Having Discrete Camera Modules and Method for Manufacturing the Same
Random Access to Wireless Network
Hardware Apparatuses and Methods to Check Data Storage Devices for Transient Faults
Electronic Device to Be Directly Charged by a Charging Device
Capacitive Wordline Boosting
Hardware Apparatuses and Methods to Perform Transactional Power Management
Backchannel Communications For Initialization of High-Speed Networks
Secure routing of trusted software transactions in unsecure fabric
Method and apparatus for making p-channel thin film transistors for oled and led active matrix flat panel displays
Patent:
9,559,215 →
Application:
14/757,875 →
Precision Time Management (Ptm) for Usb Retimers That Accurately Adjusts Timestamp Fileds of Isochronous Timestamp Packets (Itps)
Apparatus, System and Method of Controlling Data Flow Over a Communication Network
Downlink Power Management
Facial Expression Based Avatar Rendering in Video Animation and Method
Making a Defect Free Fin Based Device in Lateral Epitaxy Overgrowth Region
Electronic Assembly That Includes Stacked Electronic Devices
Interconnect Structure Comprising Fine Pitch Backside Metal Redistribution Lines Combined with Vias
Facial Liveness Detection in Image Biometrics
Spoofing Detection in Image Biometrics
Prioritized Synchronization Signals and Mechanism for Distributed Device-to-Device Systems
Facial Spoofing Detection in Image Based Biometrics
Non-Planar Semiconductor Device Having Doped Sub-Fin Region and Method to Fabricate Same
Access Network Discovery and Selection
Cell Positioning in Cellular Network
Apparatus, System and Method of Wireless Power Transfer
Cmos-Compatible Polycide Fuse Structure and Method of Fabricating Same
Automated Quality Assessment of Physiological Signals
Directed Per Bank Refresh Command
No-Reference Image and Video Quality Evaluation
Human Head Detection in Depth Images
Posting Interrupts to Virtual Processors
Interlayer Dielectric for Non-Planar Transistors
Electronic Programming Guide with Selectable Categories
Electronic Programming Guide with Selectable Categories
System and Method for the Distribution of Software Products
System and Method for the Distribution of Software Products
System and Method for the Distribution of Software Products
System and Method for the Distribution of Software Products
System and Method for the Distribution of Software Products
Packet Processing on Graphics Processing Units Using Continuous Threads
Wireless Access Point with Digital Television Capabilities
Method for Reducing Power Consumption in Solid-State Storage Device
Apparatus for Reducing Write Minimum Supply Voltage for Memory
Methods of Providing Dielectric to Conductor Adhesion in Package Structures
Recessed and Embedded Die Coreless Package
Contact Techniques and Configurations for Reducing Parasitic Resistance in Nanowire Transistors
Transducer Access Point
Application:
14/831,675 →
Publication:
US 2015/0359038
Sketch Aided Route Selection for Navigation Devices and Applications
3D Interconnect Structure Comprising Through-Silicon Vias Combined with Fine Pitch Backside Metal Redistribution Lines Fabricated Using a Dual Damascene Type Approach
Apparatus for a Monotonic Delay Line, Method for Fast Locking of a Digital Dll with Clock Stop/Start Tolerance, Apparatus and Method for Robust Clock Edge Placement, and Apparatus and Method for Clock Offset Tuning
Thermally and Electrically Conductive Structure, Method of Applying a Carbon Coating to Same, and Method of Reducing a Contact Resistance of Same
Interconnects with Fully Clad Lines
Memory Device Including Encoded Data Line-Multiplexer
Integrating a Power Arbiter in a Processor
Antenna Beam Training and Tracking Protocol for 60GHZ Operation
Cryptographic Cache Lines for a Trusted Execution Environment
Supply Margining Method and Apparatus
Variable Weak Leaker Values During Read Operations
Patent:
9,583,176 →
Application:
14/864,435 →
System and Method for Execution of a Secured Environment Initialization Instruction
Sense Amplifier
Projector Distortion Compensation in Structured Light Depth Reconstruction
Preventing Face-Based Authentication Spoofing
Dynamic Adaptive Clocking for Non-Common-Clock Interfaces
Method and System of 3D Image Capture with Dynamic Cameras
Patent:
9,445,081 →
Application:
14/866,523 →
Systems, Methods, and Apparatuses for Implementing Multi-Lens Array Cameras and Mounts
Methods and Arrangements for Frequency Selective Transmission
Directional Transmission Techniques
Controlling Operating Frequency Of A Core Domain Via A Non-Core Domain Of A Multi-Domain Processor
Multiple Device Noise Reduction Microphone Array
Sequential Circuit with Error Detection
Surface Finishes for Interconnection Pads in Microelectronic Structures
Method and Device for Processing Digital Image, and Computer-Readable Recording Medium
Die Assembly on Thin Dielectric Sheet
Application:
14/886,452 →
Publication:
US 2016/0043056
Apparatus and Method to Optimize Stt-Mram Size and Write Error Rate
Ge and III-V Channel Semiconductor Devices having Maximized Compliance and Free Surface Relaxation
Isolation Well Doping with Solid-State Diffusion Sources for Finfet Architectures
Germanium-Based Quantum Well Devices
Mechanism for Facilitating Power Extension Service at Computing Devices by One or More Power Saving Techniques
Battery Charger With USB Type-C Adapter
Flexible Command Addressing for Memory
Application:
14/926,860 →
Publication:
US 2016/0254036
Embedded Package in Pcb Build Up
Method and System of Audio Quality and Latency Adjustment for Audio Processing by Using Audio Feedback
Method, System, and Apparatus for Dynamic Thermal Management
Hybrid Carbon-Metal Interconnect Structures
Dynamically Updating At Least One Power Management Operational Parameter Pertaining To A Turbo Mode Of A Processor For Increased Performance
Register Files Including Distributed Capacitor Circuit Blocks
Patent:
9,552,854 →
Application:
14/937,010 →
Dynamic Control of Reduced Voltage State of Graphics Controller Component of Memory Controller
Stress in Trigate Devices Using Complimentary Gate Fill Materials
Iris Recognition Including Liveness Testing
Patent:
9,594,969 →
Application:
14/945,652 →
High Voltage Field Effect Transistors
Dual-Port Static Random Access Memory (Sram)
Apparatus and Method for Reducing Di/Dt During Power Wake-Up
Efficient and Scalable Intra Video/Image Coding Using Wavelets and Avc, Modified Avc, Vpx, Modified Vpx, or Modified Hevc Coding
Power Supply
Efficient, Compatible, and Scalable Intra Video/Image Coding Using Wavelets and Hevc Coding
Method and Apparatus for a Zero Voltage Processor Sleep State
Powering Unpowered Objects for Tracking, Augmented Reality, and Other Experiences
Detection of Return Oriented Programming Attacks
Memory Device Responding to Device Commands for Operational Controls
Method and Apparatus for a Zero Voltage Processor Sleep State
Bidirectional Cryptographic Io for Data Streams
Generation of Synthetic 3-Dimensional Object Images for Recognition Systems
Stacked Wafer Lens and Camera
Device Control for Wireless Charging
Apparatus and Method to Support a Storage Mode Over a Cache-Line Memory Interface to a Non-Volatile Memory Dual in Line Memory Module
Optimizing Power Usage by Factoring Processor Architectural Events to Pmu
Application:
14/972,765 →
Publication:
US 2016/0195913
Object of Interest Based Image Processing
Systems, Methods and Devices for Work Placement on Processor Cores
Through-Mold Structures
Application:
14/973,184 →
Publication:
US 2017/0178990
Electromagnetic Interference Shields for Electronic Packages and Related Methods
Regulated Load Modulation Circuit and Method for Producing Regulated Load Modulation Signaling
Dram Data Path Sharing via a Split Local Data Bus
Non-Volatile Ferroelectric Logic with Granular Power-Grating
Apparatus and Method for Shared Least Recently Used (Lru) Policy Between Multiple Cache Levels
Biometric Cryptography Using Micromachined Ultrasound Transducers
Scanning of a Handheld Object for 3-Dimensional Reconstruction
Patent:
9,639,943 →
Application:
14/976,021 →
Memory Circuit and Method for Operating a First and a Second Set of Memory Cells in Direct Memory Access Mode with Refresh
Vehicle Assistance Systems and Methods Utilizing Vehicle to Vehicle Communications
Technologies for Managing an Operational Characteristic of a Solid State Drive
Systems and Method for Selling Content Over a Network
High Stability Spintronic Memory
Methods and Systems to Selectively Boost an Operating Voltage of, and Controls to an 8T Bit-Cell Array and/or Other Logic Blocks
Mobile Device and Geographic Information System Background and Summary of the Related Art
Balancing Energy Barrier Between States in Perpendicular Magnetic Tunnel Junctions
Method for Orienting Solder Balls on a Bga Device
Dynamically Rebalancing Graphics Processor Resources
Application Scheduling in Heterogeneous Multiprocessor Computing Platforms
Application:
14/995,198 →
Publication:
US 2016/0132354
Method and apparatus for controlling screen by tracking head of user through camera module, and computer-readable recording medium therefor
Stereo depth camera using vcsel with spatially and temporally interleaved patterns
Transform Unit Size Determination for Video Coding
Pci Express Tunneling Over a Multi-Protocol I/O Interconnect
Method, Apparatus, And System For Optimizing Frequency And Performance In A Multidie Microprocessor
Refresh Parameter-Dependent Memory Refresh Management
Spin Transfer Torque Based Memory Elements for Programmable Device Arrays
Systems and Methods for Interference Mitigation in Heterogeneous Networks
Runtime Dispatching Among a Hererogeneous Groups of Processors
CMOS FinFET Device with Dual Strained Cladding Layers on Relaxed SiGe Fins, and Method of Fabricating the Same
Autonomously Controlling a Buffer of a Processor
Digital Synthesizable Low Dropout Regulator with Adaptive Gain
Apparatus for Charge Recovery During Low Power Mode
Control of Output Power of a Battery Charger for Charging a Battery of an Electronic Device from an Energy Source
Hybrid Memory and Mtj Based Mram Bit-Cell and Array
Bi-Axial Tensile Strained Ge Channel for Cmos
Pre-Sculpting of Si Fin Elements Prior to Cladding for Transistor Channel Applications
Predicting Future Power Level States For Processor Cores
Vertical Nanowire Transistor with Axially Engineered Semiconductor and Gate Metallization
System and Method for Electronically Tagging Items for Use in Controlling Electrical Devices
Strained Channel Region Transistors Employing Source and Drain Stressors and Systems Including the Same
Filter for Network Intrusion and Virus Detection
Land Side and Die Side Cavities to Reduce Package Z-Height
Method for Fabricating Transistor with Thinned Channel
Reduced Swing Bit-Line Apparatus and Method
Content Adaptive Telecine and Interlace Reverser
Method and Apparatus to Process 4-Operand SIMD Integer Multiply-Accumulate Instruction
Indicating Critical Battery Status in Mobile Devices
Memory Channel That Supports Near Memory and Far Memory Access
Device, System and Method of Scheduling Communications with a Group of Wireless Communication Units
Usb Interface Using Repeaters with Guest Protocol Support
Cellular Flexible Battery Cells
Method and Apparatus for Dynamically Adjusting Voltage Reference to Optimize an I/O System
Position Determination and Control with Radio Frequency Identification Tags
Patent:
9,704,003 →
Application:
15/088,518 →
Internet of Things Battery Device
Method and Apparatus for Bluetooth-Based General Service Discovery
On Demand Customization of Mobile Computing Devices
Direct Plasma Densification Process and Semiconductor Devices
Real-Time 3D Reconstruction with a Depth Camera
Apparatus for Adaptive Write Assist for Memory
Fin Sculpting and Cladding During Replacement Gate Process for Transistor Channel Applications
Techniques for Forming Spin-Transfer Torque Memory Having a Dot-Contacted Free Magnetic Layer
Antifuse Element Using Spacer Breakdown
Aspect Ratio Trapping (Art) for Fabricating Vertical Semiconductor Devices
Solid-Source Diffused Junction for Fin-Based Electronics
Modulation of Magnetic Properties Through Implantation and Associated Structures
Non-Planar Semiconductor Device Having Omega-Fin with Doped Sub-Fin Region and Method to Fabricate Same
Techniques for Forming Vertical Transistor Architectures
Avatar Animation System
Ge/Sige-Channel and Iii-V-Channel Transistors on the Same Die
Methods, Systems, and Devices for Network-Provided Autonomous Handover
Seam Healing of Metal Interconnects
Spin-Transfer Torque Memory (Sttm) Devices Having Magnetic Contacts
Scalable Real-Time Face Beautification of Video Images
Multi-Gate Transistor with Variably Sized Fin
Etchstop Layers and Capacitors
Non-Planar Semiconductor Device Having Group Iii-V Material Active Region with Multi-Dielectric Gate Stack
Synthesis of Transformed Image Views
Solder Attach Apparatus and Method
Application:
15/137,860 →
Publication:
US 2016/0240506
Techniques for Adding Interactive Features to Videos
Apparatus for Data Retention and Supply Noise Mitigation Using Clamps
Patent:
9,766,827 →
Application:
15/151,402 →
Techniques for Enhancing Fracture Resistance of Interconnects
Multiport Memory Cell Having Improved Density Area
Application:
15/157,158 →
Publication:
US 2016/0260475
Device, System and Method for Communication with Heterogeneous Physical Layers
Negative Bitline Write Assist Circuit and Method for Operating the Same
Apparatus, System, and Method for Persistent User-Level Thread
Integrated Inductor for Integrated Circuit Devices
System and Method for Controlling Home Network Devices Using Multicast Enabled Remote Controls
Application:
15/171,963 →
Publication:
US 2016/0360284
High Density Package Interconnects
Zero-Power Mode
Mobile Platform Software Update with Secure Authentication
Semiconductor Device Structures and Methods of Forming Semiconductor Structures
Voltage Level Shifter Circuit
Digital Phase Controlled Delay Circuit
Performance of Additional Refresh Operations During Self-Refresh Mode
Apparatus to Reduce Retention Failure in Complementary Resistive Memory
Processor Having Accelerated User Responsiveness In Constrained Environment
Battery Utilizing Device Cavity
Self-Forming, Self-Aligned Barriers for Back-End Interconnects and Methods of Making Same
Application:
15/192,643 →
Publication:
US 2016/0307796
Hardware Accelerator for Platform Firmware Integrity Check
Technologies for Provisioning and Managing Secure Launch Enclave with Platform Firmware
Platform and Processor Power Management
Efficient Low Cost on-Die Configurable Bridge Controller
Hand Gesture Recognition for Cursor Control
Interprocessor Power State Transitions
Road Condition Heads Up Display
Systems and Methods for Mixed Reality Transitions
Method of Forming High Density, High Shorting Margin, and Low Capacitance Interconnects by Alternating Recessed Trenches
Method and Apparatus for Efficient Store/Restore of State Information During a Power State Transition
Multichip Integration with Through Silicon via (Tsv) Die Embedded in Package
Techniques for Improving Stereo Block Matching with the Pyramid Method
Application:
15/213,326 →
Publication:
US 2017/0171524
Substrate Conductor Structure and Method
Backchannel Communications For Initialization of High-Speed Networks
Techniques for Forming Interconnects in Porous Dielectric Materials
Generating Multiple Secure Hashes from a Single Data Buffer
Instruction for Accelerating Snow 3G Wireless Security Algorithm
Energy Storage Device, Method of Manufacturing Same, and Mobile Electronic Device Containing Same
Method and System of 3D Image Capture with Dynamic Cameras
Grid Array Connection Device and Method
Mobile Systems with Seamless Transition by Activating Second Subsystem to Continue Operation of Application Executed by First Subsystem as It Enters Sleep Mode
Hybrid Phase Field Effect Transistor
Stress in Trigate Devices Using Complimentary Gate Fill Materials
Contact Techniques and Configurations for Reducing Parasitic Resistance in Nanowire Transistors
Interconnects Having Sealing Structures to Enable Selective Metal Capping Layers
Dyanamically Adapting a Voltage of a Clock Generation Circuit
Distribution of Tasks Among Asymmetric Processing Elements
Distribution of Tasks Among Asymmetric Processing Elements
Distribution of Tasks Among Asymmetric Processing Elements
Apparatus and Method for Vector Instructions for Large Integer Arithmetic
Integrated Circuit Package Substrate
Collaborative Processor and System Performance and Power Management
Apparatus and Method for Flushing Dirty Cache Lines Based on Cache Activity Levels
Apparatuses and Methods for Reducing Switching Jitter
Digital Advertising System
Germanium-Based Quantum Well Devices
Providing Limited Access to a Service Device via an Intermediary
Virtual Guard Rails
Semiconductor Interconnect Structures
Systems and Methods for Accessing a Unified Translation Lookaside Buffer
Technologies for Communicating Roadway Information
Method And Apparatus For A Zero Voltage Processor Sleep State
Low Resistance Bitline and Sourceline Apparatus for Improving Read and Write Operations of a Nonvolatile Memory
Optimizing Power Usage by Factoring Processor Architectural Events to Pmu
Application:
15/281,506 →
Publication:
US 2017/0017292
Optimizing Power Usage by Factoring Processor Architectural Events to Pmu
High Speed I/O Pinless Structural Testing
Apparatuses, Methods, and Systems for Dense Circuitry Using Tunnel Field Effect Transistors
Systems, Methods, and Apparatuses for Implementing Die Recovery in Two-Level Memory (2LM) Stacked Die Subsystems
Accessing Memory Coupled to a Target Node from an Initiator Node
Selective Memory Mode Authorization Enforcement
Power Management Techniques For Wirelessly-Interconnected Devices
Method to Reuse the Pulse Discharge Energy During Li-Ion Fast Charging for Better Power Flow Efficiency
Techniques for Use of Vendor Defined Messages to Execute a Command to Access a Storage Device
Application:
15/289,878 →
Publication:
US 2017/0249281
Boundary Scan Chain for Stacked Memory
Integrated Circuit Package
Hardware Apparatuses and Methods to Control Access to a Multiple Bank Data Cache
Facilitating Environment-Based Lossy Compression of Data for Efficient Rendering of Contents at Computing Devices
Coupled Spin Hall Nano Oscillators with Tunable Strength
One Measurement Gap in Asynchronous Dual Connectivity
Programmable Memory Device Sense Amplifier
Providing Secure Data Transmission Over a Universal Serial Bus (Usb) Interface
Non-Volatile Storage for Graphics Hardware
Method, System, and Device for Selecting and Displaying Information on a Mobile Digital Display Device
Instruction for Fast Zuc Algorithm Processing
Apparatus, System and Method of Communicating Multicast Traffic
Power Consumption Monitoring Device for a Power Source
Single-Package Wireless Communication Device
Determining a High Data Rate for Backchannel Communications for Initialization of High-Speed Networks
Method, Apparatus and System for Dynamic Clock Frequency Control on a Bus
Memory Circuitry with Row-Wise Gating Capabilities
Patent:
9,916,889 →
Application:
15/366,951 →
Designs and Methods for Conductive Bumps
Latched Comparator Circuit
Recessed and Embedded Die Coreless Package
System And Method For Controlling Home Network Devices Using Multicast Enabled Remote Controls
Application:
15/376,164 →
Publication:
US 2017/0094369
Power Switching Circuitry Including Power-Up Control
Method and System of Self-Calibration for Phase Detection Autofocus
Apparatus, System, And Method For Persistent User-Level Thread
Apparatuses, Methods, and Systems for Increasing a Speed of Removal of Data from a Memory Cell
Interactive Delivery of Media Using Dynamic Playlist Generation Subject to Restrictive Criteria
Application:
15/390,271 →
Publication:
US 2017/0111416
Integrated Circuit Interconnect Structure Having Metal Oxide Adhesive Layer
Battery Charge Level Based Mobile Navigation System
Determining Demarcation Voltage via Timestamps
Patent:
9,934,859 →
Application:
15/391,763 →
Land Grid Array Package Extension
Detection of Traffic Dynamics and Road Changes in Autonomous Driving
Apparatuses and Methods for Accessing and Scheduling Between a Plurality of Row Buffers
Trusted Timer Service
Positionally Aware Communication with Multiple Storage Devices Over a Multi-Wire Serial Bus
Electronic Package Assembly with Compact Die Placement
Apparatus, System and Method to Determine a Demarcation Voltage to Use to Read a Non-Volatile Memory
Mechanism for Facilitating Power Extension Service at Computing Devices by One or More Power Saving Techniques
Balancing Power Supply and Demand
Universal Serial Bus Type-C Power Delivery
Multi-Core Shared Page Miss Handler
Multi-Core Shared Page Miss Handler
Multi-Core Shared Page Miss Handler
Computing Performance and Power Management with Firmware Performance Data Structure
Apparatus for Improving Read Stability
Patent:
9,922,702 →
Application:
15/397,035 →
Hand Gesture Recognition for Virtual Reality and Augmented Reality Devices
Efficient Gesture Processing
Method and Apparatus to Process 4-Operand SIMD Integer Multiply-Accumulate Intruction
Detection of Return Oriented Programming Attacks
Interlayer Dielectric for Non-Planar Transistors
Enhancing Ps-Poll for Low-Power Wifi
Application:
15/401,666 →
Publication:
US 2017/0347318
System and Method for Execution of a Secured Environment Initialization Instruction
System and Method for Execution of a Secured Environment Initialization Instruction
System and Method for Execution of a Secured Environment Initialization Instruction
Computing Platform with Interface Based Error Injection
Ge and Iii-V Channel Semiconductor Devices Having Maximized Compliance and Free Surface Relaxation
Semiconductor Device Having Metallic Source and Drain Regions
Instructions to Mark Beginning and End of Non Transactional Code Region Requiring Write Back to Persistent Storage
Dielectric and Isolation Lower Fin Material for Fin-Based Electronics
Doping with Solid-State Diffusion Sources for Finfet Architectures
Wireless Transmission Over Space-Time Channels
Register Files Including Distributed Capacitor Circuit Blocks
Technologies for Assisting Vehicles with Changing Road Conditions
Land Side and Die Side Cavities to Reduce Package Z-Height
Serial Bus Electrical Termination Control
Methods and Apparatus for Reusing Lookup Table Random-Access Memory (Lutram) Elements as Configuration Random-Access Memory (Cram) Elements
Patent:
9,940,995 →
Application:
15/421,098 →
Low Power Circuit for Transistor Electrical Overstress Protection in High Voltage Applications
Sequential Circuit with Error Detection
Formation of Dram Capacitor Among Metal Interconnect
Application:
15/425,596 →
Publication:
US 2017/0148868
Conductive Paths Through Dielectric with a High Aspect Ratio for Semiconductor Devices
Etchstop Layers and Capacitors
Making a Defect Free Fin Based Device in Lateral Epitaxy Overgrowth Region
Compressed Instruction Format
Semiconductor Device with Isolated Body Portion
System and Method for Interacting with Digital Signage
File Encryption, Decryption and Accessvia Near Field Communication
High Density Interconnect Device and Method
Digitally Trimmable Integrated Resistors Including Resistive Memory Elements
Probabilistic Inventory Rfid Method and System
Method and Apparatus for Selective Deep Scan Using a Motion Sensor Co-Located with Rfid Reader
Sense Amplifier
Methods and Arrangements for Frequency Selective Transmission
Hardware Apparatuses and Methods to Check Data Storage Devices for Transient Faults
Apparatus and Method for Implementing a Multi-Level Memory Hierarchy
Presenting Advertisements During Media Content Seek
System, Methods, and Apparatus for in-Vehicle Fiducial Mark Tracking and Interpretation
Mobile Augmented Reality System
Adaptive Read Technique for Multi-Drop Bus
Multiply Add Functional Unit Capable of Executing Scale, Round, Getexp, Round, Getmant, Reduce, Range and Class Instructions
Gesture Pre-Processing of Video Stream Using a Markered Region
Time Tracking with Trits
A Stacked Semiconductor Package Having Fault Detection and a Method for Identifying a Fault in a Stacked Package
Stacked Semiconductor Package and Method for Performing Bare Die Testing on a Functional Die in a Stacked Semiconductor Package
Systems, Methods, and Apparatuses for Implementing Testing of a Far Memory Subsystem Within Two-Level Memory (2LM) Stacked Die Subsystems
Multiple Storage Devices Implemented Using a Common Connector
Dynamic Pixel Density Adjustment
Memory Channel That Supports Near Memory and Far Memory Access
Wearable Sensor Data to Improve Map and Navigation Data
Application:
15/483,288 →
Publication:
US 2018/0066959
Non-Planar Semiconductor Device Having Group Iii-V Material Active Region with Multi-Dielectric Gate Stack
Methods and Apparatus for Detecting Defects in Memory Circuitry
Pre-Sculpting of Si Fin Elements Prior to Cladding for Transistor Channel Applications
Flexible Command Addressing for Memory
Apparatus, System and Method for Caching Compressed Data
Timing Control for Unmatched Signal Receiver
Device-To-Device (D2D) Communications
Bitcell State Retention
Methods and Systems to Selectively Boost an Operating Voltage of, and Controls to an 8T Bit-Cell Array and/or Other Logic Blocks
Intelligent Vehicle Navigator
Trajectory Planning for Video Stabilization
Fabrication of Crystalline Magnetic Films for Psttm Applications
Amorphous Seed Layer for Improved Stability in Perpendicular Sttm Stack
Magnetic Diffusion Barriers and Filter in Psttm Mtj Construction
Access Control Mechanisms for D2D Discovery and Communication
Strain Assisted Spin Torque Switching Spin Transfer Torque Memory
High Mobility Nanowire Fin Channel on Silicon Substrate Formed Using Sacrificial Sub-Fin
Optimizing Gate Profile for Performance and Gate Fill
Underlying Absorbing or Conducting Layer for Ebeam Direct Write (Ebdw) Lithography
Decoupled via Fill
Via Blocking Layer
Workload Scheduler for Computing Devices with Camera
Methods and Apparatus for Reducing Energy Consumed by Drones During Flight
Ferroelectric Based Memory Cell with Non-Volatile Retention
Restricting Current Draw in Wearable Devices
Metallic Spin Super Lattice for Logic and Memory Devices
Transition Metal Dry Etch by Atomic Layer Removal of Oxide Layers for Device Fabrication
Inherently Selective Precursors for Deposition of Second or Third Row Transition Metal Thin Films
Techniques for Forming Transistors on the Same Die with Varied Channel Materials
Integrating Mems Structures with Interconnects and Vias
Textile Patterning for Subtractively-Patterned Self-Aligned Interconnects, Plugs, and Vias
Sub-Fin Sidewall Passivation in Replacement Channel Finfets
Semi-Volatile Embedded Memory with Between-Fin Floating-Gate Device and Method
Transistor Fin Formation via Cladding on Sacrificial Core
ENHANCED PROXIMITY SERVICES (ProSe) PROTOCOLS FOR VEHICLE-TO-ANYTHING (V2X) COMMUNICATION
Methods and Apparatus for Battery Current Monitoring
Integrated Inductor for Integrated Circuit Devices
Wireless Communication System to Communicate Using Different Beamwidths
Mechanism for Facilitating Power Extension Service at Computing Devices by One or More Power Saving Techniques
Memory Elements with Soft-Error-Upset (Seu) Immunity Using Parasitic Components
Logic Chip Including Embedded Magnetic Tunnel Junctions
Navigation Systems and Associated Methods
Solder Resist Layers for Coreless Packages and Methods of Fabrication
ASSISTANCE INFORMATION FOR EVOLVED NODE B (eNB) PARAMETER TUNING
Apparatus, System and Method of Indicating a Time Offset Using a Grant Frame
Changing Cache Ownership in Clustered Multiprocessor
High Voltage Field Effect Transistors
Strained Channel Region Transistors Employing Source and Drain Stressors and Systems Including the Same
Ram-Based Shift Register with Embedded Addressing
Patent:
10,102,892 →
Application:
15/611,070 →
Package Assembly for Embedded Die and Associated Techniques and Configurations
Directed Per Bank Refresh Command
In-Lane Vector Shuffle Instructions
Hybrid Carbon-Metal Interconnect Structures
Electronic Device to Be Directly Charged by a Charging Device
Direct Plasma Densification Process and Semiconductor Devices
Aggregated Analytics for Intelligent Transportation Systems
User Interchangeable Ornamental Portions of Electronic Devices
Route Selection for Navigation Devices and Applications
Apparatus, System and Method of Neighbor Awareness Networking (Nan) Geo-Fencing
I/O Layout Footprint for Multiple 1LM/2LM Configurations
Memory circuits and methods for distributed memory hazard detection and error recovery
Patent:
10,515,049 →
Application:
15/640,541 →
Parking Management System and Method
Access Network Discovery and Selection
Dynamically Associated Neighbor Awareness Networking (Nan) Discovery Windows for Fine Timing Measurement
Pedestrian Crossing and/or Traffic Light Control Method and Apparatus
Land Side and Die Side Cavities to Reduce Package Z-Height
Methods, Systems and Apparatus to Improve Radio Frequency Identification (Rfid) Tag Communication
Performance of Additional Refresh Operations During Self-Refresh Mode
Self-Aligned 3-D Epitaxial Structures for Mos Device Fabrication
Controlling Temperature Of A System Memory
Magnetic Field-Assisted Memory Operation
Application:
15/676,964 →
Publication:
US 2018/0025764
Hardware Apparatuses and Methods to Perform Transactional Power Management
Systems and Methods for Accessing a Unified Translation Lookaside Buffer
Multiband Central Controller and Method for Multiband Network Operations
Polarity Based Data Transfer Function for Volatile Memory
Determining a High Data Rate for Backchannel Communications for Initialization of High-Speed Networks
Selectively Augmenting Communications Transmitted by a Communication Device
Application:
15/688,294 →
Publication:
US 2018/0203584
Technologies for Fast Low-Power Startup of a Computing Device
Stacked Memory with Interface Providing Offset Interconnects
Application:
15/699,750 →
Publication:
US 2018/0122779
Apparatus for Data Retention and Supply Noise Mitigation Using Clamps
Recessed and Embedded Die Coreless Package
Application:
15/711,880 →
Publication:
US 2018/0012871
Efficient Frame Loss Recovery and Reconstruction in Dyadic Hierarchy Based Coding
Electromagnetic Interference Shields for Electronic Packages and Related Methods
Biasing Scheme for High Voltage Circuits Using Low Voltage Devices
Temporal Motion Vector Prediction Control in Video Coding
System for Improved Power Distribution to a Memory Card Through Remote Sense Feedback
Secure Memory Repartitioning Technologies
SYSTEMS AND METHODS FOR MIXED INSTRUCTION MULTIPLE DATA (xIMD) COMPUTING
Modular Interconnection Repair of Multi-Die Package
Patent:
10,079,211 →
Application:
15/719,303 →
Semiconductor devices, and a Method for Forming a Semiconductor device
Forming a Non-Planar Transistor Having a Quantum Well Channel
Detecting Mobile Device Sensor Malfunctions
Package Substrate First-Level-Interconnect Architecture
Patent:
10,121,679 →
Application:
15/721,384 →
Method and Apparatus for Adjusting Demarcation Voltages Based on Cycle Count Metrics
Bidirectional Power Management Techniques
Memory Module Thermal Management
Method and System of Image Distortion Correction for Images Captured by Using a Wide-Angle Lens
Method for Fabricating Transistor with Thinned Channel
Capped Magnetic Memory
Perpendicular Magnetic Memory with Filament Conduction Path
Perpendicular Magnetic Memory with Reduced Switching Current
Low Stray Field Magnetic Memory
Architecture to Communicate Signals for Operating a Static Random Access Memory
Spin Transfer Torque Memory (Sttm), Methods of Forming the Same Using Volatile Compound Forming Elements, and Devices Including the Same
Inorganic Interposer for Multi-Chip Packaging
High Retention Resistive Random Access Memory
Heat Spreaders with Interlocked Inserts
Low Resistance Interconnect
Metal-Oxide-Polysilicon Tunable Resistor for Flexible Circuit Design and Method of Fabricating Same
Docking Station
Latency Reduction for Wireless Data Transmission
Semiconductor Devices Having Ruthenium Phosphorus Thin Films
Forming Interconnects with Self-Assembled Monolayers
Electrical device and a method for forming an electrical device
Improved Package Power Delivery Using Plane and Shaped Vias
Transistor with a Sub-Fin Dielectric Region Under a Gate
Reduced Leakage Transistors with Germanium-Rich Channel Regions
Crystallized Silicon Carbon Replacement Material for Nmos Source/Drain Regions
Electronic Package That Includes Lamination Layer
Methods of Forming Doped Source/Drain Contacts and Structures Formed Thereby
Projecting Contacts and Method for Making the Same
In-Lane Vector Shuffle Instructions
Controlling Power Delivery To A Processor Via A Bypass
Negative Bitline Write Assist Circuit and Method for Operating the Same
Memory Circuit and Method for Operating a First Mram and a Second Mram Set of Memory Cells Configured to Operate in a Direct Access Mode and/or Refresh Mode
Integrated Circuit Package Substrate
Discovery Mechanisms for Universal Serial Bus (Usb) Protocol Adaptation Layer
Application:
15/817,788 →
Publication:
US 2018/0181517
Signaling a Synchronization Frame Transmission Request
Patent:
50,750 →
Application:
15/823,368 →
Bi-Directional Community Information Brokerage
Application:
15/825,544 →
Publication:
US 2018/0307892
Inferred Undocking for Hybrid Tablet Computer
Color Parameter Adjustment Based on the State of Scene Content and Global Illumination Changes
Ring-In-Ring Configurable-Capacitance Stiffeners and Methods of Assembling Same
Electronic Packages with Stacked Sitffeners and Methods of Assembling Same
Light Pattern Based Vehicle Location Determination Method and Apparatus
Methods and Arrangements for Vehicle-to-Vehicle Communications
In-Lane Vector Shuffle Instructions
In-Lane Vector Shuffle Instructions
In-Lane Vector Shuffle Instructions
An Electronic Power Device with Protection Cover
Unblock Instruction to Reverse Page Block During Paging
Electronic Device to Be Directly Charged by a Charging Device with a Protection Mechanism
Mechanism for Extending Cycle Life of a Battery
Negative Bitline Write Assist Circuit and Method for Operating the Same
Folding Devices
Method and Apparatus to Efficiently Perform Filter Operations for an in-Memory Relational Database
Methods and Systems for Performing a Calculation Across a Memory Array
Estimation of Illumination Chromaticity in Automatic White Balancing
Memory Channel That Supports Near Memory and Far Memory Access
Navigation Systems and Associated Methods
Navigation Systems and Associated Methods
Navigation Systems and Associated Methods
Dual-Damascene Zero-Misalignment-via Process for Semiconductor Packaging
Stacked Semiconductor Architecture Including Semiconductor Dies and Thermal Spreaders on a Base Die
Detecting Fatigue Based on Electroencephalogram (Eeg) Data
LOWER IC PACKAGE STRUCTURE FOR COUPLING WITH AN UPPER IC PACKAGE TO FORM A PACKAGE-ON-PACKAGE (PoP) ASSEMBLY AND PoP ASSEMBLY INCLUDING SUCH A LOWER IC PACKAGE STRUCTURE
Cryptographic Cache Lines for a Trusted Execution Environment
Memory Device Including Encoded Data Line-Multiplexer
Spoofing Detection in Image Biometrics
Techniques for Forming Spin-Transfer Torque Memory Having a Dot-Contacted Free Magnetic Layer
Dielectric and Isolation Lower Fin Material for Fin-Based Electronics
Via Blocking Layer
Compacted Context State Management
Computing Performance and Power Management with Firmware Performance Data Structure
High Density Package Interconnects
Serial Bus Electrical Termination Control
Method of Forming High Density, High Shorting Margin, and Low Capacitance Interconnects by Alternating Recessed Trenches
Integrated Error Checking and Correction (Ecc) in Byte Mode Memory Devices
Retractable Displays for Helmets
Cobalt Based Interconnects and Methods of Fabrication Thereof
Antifuse Element Using Spacer Breakdown
System, Apparatus And Method For Providing Hardware Feedback Information In A Processor
Supplemental Power Reception by Bypassing Voltage Regulator
Vehicle Slack Distribution
Dram Data Path Sharing via a Split Local Data Bus
Methods and Apparatus to Offload Media Streams in Host Devices
Mobile Augmented Reality System
Pci Express Tunneling Over a Multi-Protocol I/O Interconnect
Reconfigurable Processing Unit
One-Sided Soft Reads
Bowl-Shaped Imaging System
Interprocessor Power State Transitions
Charge-Saving Power-Gate Apparatus and Method
Logic Chip Including Embedded Magnetic Tunnel Junctions
Dynamic Adaptive Clocking for Non-Common-Clock Interfaces
Methods and Systems for Motion Vector Derivation at a Video Decoder
Grid Array Connection Device and Method
Circuits for Digital and Analog Controlled Oscillators
Two-Wire Link for Time-Multiplexed Power and Data Transmission to Multiple Devices
Platform Power Consumption Reduction via Power State Switching
Mobile Systems with Seamless Transition by Activating Second Subsystem to Continue Operation of Application Executed by First Subsystem as It Enters Sleep Mode
Through-Mold Structures
Pre-Sculpting of Si Fin Elements Prior to Cladding for Transistor Channel Applications
Providing Dead-Block Prediction for Determining Whether to Cache Data in Cache Devices
Vehicular occupancy assessment
Application:
15/999,609 →
Publication:
US 2019/0054842
User-To-User Communication Enhancement with Augmented Reality
Application:
16/000,741 →
Publication:
US 2018/0286137
Decoupled via Fill
Controls and Indicators with on-Screen Cognitive Aids
Multi-Packaging for Single-Socketing
Package Assembly for Embedded Die and Associated Techniques and Configurations
Inter Electric Vehicle Charge Transfer
Electromigration Resistant and Profile Consistent Contact Arrays
Patent:
10,431,537 →
Application:
16/014,134 →
Apparatus and Method for Conservative Morphological Antialiasing with Multisampling
Speeding Up Small Block Intra-Prediction in Video Coding
Package-Embedded Thin-Film Capacitors, Package-Integral Magnetic Inductors, and Methods of Assembling Same
Patent:
10,373,951 →
Application:
16/017,247 →
Capacitors Embedded in Stiffeners for Small Form-Factor and Methods of Assembling Same
Adaptive Memory Training for Enhanced Automotive Boot
Folded Semiconductor Package Architectures and Methods of Assembling Same
Adaptive Learning Environment Driven by Real-Time Identification of Engagement Level
Traffic Management System, Components of a Distributed Traffic Management System, Prioritization/Load-Distribution System, and Methods Thereof
Functional Safety Power Supply Framework for Real-Time Automotive Systems
Diffractive Optical Elements for Wide Field-of-View Virtual Reality Devices and Methods of Manufacturing the Same
Apparatuses and Methods to Control Operations Performed on Resistive Memory Cells
Dynamic Sleep for a Display Panel
Gesture Pre-Processing of Video Stream Using a Markered Region
Interlayer Dielectric for Non-Planar Transistors
Non-Volatile Register File Including Memory Cells Having Conductive Oxide Memory Element
Memory Channel That Supports Near Memory and Far Memory Access
Seam Healing of Metal Interconnects
Systems, Methods and Devices for Work Placement on Processor Cores
Computing Platform Interface with Memory Management
Apparatus for Low Power Write and Read Operations for Resistive Memory
Generation of Synthetic 3-Dimensional Object Images for Recognition Systems
Controlling Power Delivery To A Processor Via A Bypass
Controlling Power Delivery to a Processor via a Bypass
Integrated Circuit Packages
Pitch Division Patterning Approaches with Increased Overlay Margin for Back End of Line (Beol) Interconnect Fabrication and Structures Resulting Therefrom
Interconnect Capping Process for Integration of Mram Devices and the Resulting Structures
Self-Aligned via Below Subtractively Patterned Interconnect
Geometry Tuning of Fin Based Transistor
Approaches for Strain Engineering of Perpendicular Magnetic Tunnel Junctions (Pmtjs) and the Resulting Structures
Simulating the Motion of Complex Objects in Response to Connected Structure Motion
Dopant Diffusion Barrier for Source/Drain to Curb Dopant Atom Diffusion
Techniques for Forming Logic Including Integrated Spin-Transfer Torque Magnetoresistive Random-Access Memory
Multilayer Selector Device with Low Holding Voltage
Programmable Metallization Cell with Alloy Layer
Polarization Gate Stack Sram
Substrate-Free System in Package Design
Stairstep Interposers with Integrated Shielding for Electronics Packages
Transistor Threshold Voltage Variation Optimization
Diffusion Barriers
System to Monitor Utilization of Personal Protective Equipment in Restricted Areas
Subtractive Plug and Tab Patterning with Photobuckets for Back End of Line (Beol) Spacer-Based Interconnects
Semiconductor Package Having Inductive Lateral Interconnects
A Finfet Transistor Having a Doped Subfin Structure to Reduce Channel to Substrate Leakage
Microelectronic Device Stacks Having Interior Window Wirebonding
Rram Devices and Their Methods of Fabrication
Non-Planar Semiconductor Device Having Doped Sub-Fin Region and Method to Fabricate Same
Apparatus and Method for Shared Least Recently Used (Lru) Policy Between Multiple Cache Levels
Presenting Advertisements During Media Content Seek
Device Resource Management Based on Contextual Planning
Application:
16/106,887 →
Publication:
US 2019/0140898
Vehicular Occupancy Assessment
Application:
16/107,770 →
Publication:
US 2019/0184855
Multiband Central Controller and Method for Multiband Network Operations
Power-Based Dynamic Adjustment of Memory Module Bandwidth
Apparatus, System and Method of Communicating Over a Media Agnostic (Ma) Usb Connection
Probabilistic Inventory Rfid Method and System
Application:
16/123,889 →
Publication:
US 2019/0019139
Electronic Device Including a Lateral Trace
Modular Interconnection Repair of Multi-Die Package
Substrate Conductor Structure and Method
Selective Connection for Interface Circuitry
Intelligent Vehicle Point of Focus Communication
Methods for Autonomous Authentication for Vehicle-to-Vehicle (V2V) Communications in Out-of-Coverage Scenarios
Process-Based Multi-Key Total Memory Encryption
Clock Architecture in Heterogeneous System-In-Package
Compressed Instruction Format
Technologies for Assisting Vehicles with Changing Road Conditions
Technologies for Providing Information to a User While Traveling
Per Row Activation Count Values Embedded in Storage Cell Array Storage Cells
Streaming On Diverse Transports
Recessed and Embedded Die Coreless Package
Content Adaptive Quantization for Video Coding
Directed Per Bank Refresh Command
Spin-Transfer Torque Memory (Sttm) Devices Having Magnetic Contacts
Techniques for Multi-Read and Multi-Write of Memory Circuit
Underfill Material Flow Control for Reduced Die-to-Die Spacing in Semiconductor Packages
Dynamically Associated Neighbor Awareness Networking (Nan) Discovery Windows for Fine Timing Measurement
Systems and Method for Selling Content Over a Network
Application:
16/230,515 →
Publication:
US 2019/0354946
Sensor Data Sharing Management
Module Memory and Battery Device
Collision Avoidance System, Depth Imaging System, Vehicle, Obstacle Map Generator, and Methods Thereof
Inter-Die Passive Interconnects Approaching Monolithic Performance
Integrated Circuit Interconnect Structure Having Metal Oxide Adhesive Layer
Decoupled via Fill
Wireless Communication System to Communicate Using Different Beamwidths
Upgradable Vehicular Computing Methods and Apparatuses
High Density Package Interconnects
Detection of Traffic Dynamics and Road Changes in Autonomous Driving
Designs and Methods for Conductive Bumps
Methods and Systems to Selectively Boost an Operating Voltage of, and Controls to an 8T Bit-Cell Array and/or Other Logic Blocks
Performing Power Management In A Multicore Processor
Autonomously Controlling a Buffer of a Processor
Electromagnetic Interference Shields for Electronic Packages and Related Methods
Device Control for Wireless Charging
Semiconductor Device with Released Source and Drain
Rlink - Die to Die Channel Interconnect Configurations to Improve Signaling
Dual Role Capable Connectors for Separable Portion of Computing Apparatus
Wireless Stylus with Grip Force Expression Capability
A Finfet Transistor Having a Tapered Subfin Structure
Convertible Dual Screen Laptop
Spacer-Based Patterning for Tight-Pitch and Low-Variability Random Access Memory (Ram) Bit Cells and the Resulting Structures
Techniques for Increasing Channel Region Tensile Strain in N-Mos Devices
Data Storage System Using Wafer-Level Packaging
3D Stacked-in-Recess System in Package
Package-Level Noise Filtering for Emi Rfi Mitigation
Stair-Stacked Dice Device in a System in Package, and Methods of Making Same
Prepackaged Stair-Stacked Memory Module in a Chip Scale System in Package, and Methods of Making Same
Integrated Circuit Devices with Non-Collapsed Fins and Methods of Treating the Fins to Prevent Fin Collapse
Semiconductor Package Having Integrated Stiffener Region
Perpendicular Sttm Free Layer Including Protective Cap
Overpass Dice Stacks and Methods of Using Same
Semiconductor Packaging with High Density Interconnects
Reconfigurable Thermal Control of High-Powered Integrated Circuitry
Local Interconnect for Group Iv Source/Drain Regions
Digital Synthesizable Low Dropout Regulator with Adaptive Gain
Universal Serial Bus Type-C Power Delivery
Apparatus and Method for Implementing a Multi-Level Memory Hierarchy
Spoken Keyword Detection Based Utterance-Level Wake on Intent System
Magnetic Memory Devices with Enhanced Tunnel Magnetoresistance Ratio (Tmr) and Methods of Fabrication
Methods and Apparatus for Performing Design for Debug via Protocol Interface
Method for Orienting Solder Balls on a Bga Device
Package Assembly for Embedded Die and Associated Techniques and Configurations
Integrated Circuit Package Substrate
Processor Having Accelerated User Responsiveness In Constrained Environment
Land Grid Array Package Extension
Collaborative Processor and System Performance and Power Management
Aggregated Analytics for Intelligent Transportation Systems
Obtaining Vendor Information Using Mobile Internet Devices
Inferred Undocking for Hybrid Tablet Computer
Ring-In-Ring Configurable-Capacitance Stiffeners and Methods of Assembling Same
Stiffener-Integrated Interconnect Bypasses for Chip-Package Apparatus and Methods of Assembling Same
Package-Embedded Thin-Film Capacitors, Package-Integral Magnetic Inductors, and Methods of Assembling Same
Memory Channel That Supports Near Memory and Far Memory Access
Land Side and Die Side Cavities to Reduce Package Z-Height
Automated Quality Assessment of Physiological Signals
Stacked Memory with Interface Providing Offset Interconnects
Techniques for Command Validation for Access to a Storage Device by a Remote Client
Doping with Solid-State Diffusion Sources for Finfet Architectures
Grid Array Connection Device and Method
Textile Patterning for Subtractively-Patterned Self-Aligned Interconnects, Plugs, and Vias
Dielectric and Isolation Lower Fin Material for Fin-Based Electronics
Non-Planar Semiconductor Device Having Omega-Fin with Doped Sub-Fin Region and Method to Fabricate Same
Multiply Add Functional Unit Capable of Executing Scale, Round, Getexp, Round, Getmant, Reduce, Range and Class Instructions
Persistent Universal Serial Bus (Usb) Device Enumeration
Methods and Apparatus for Reducing Energy Consumed by Drones During Flight
Retractable Displays for Helmets
Microelectronic Devices Having Air Gap Structures Integrated with Interconnect for Reduced Parasitic Capacitances
Perpendicular Spin Transfer Torque Memory (Psttm) Devices with Enhanced Perpendicular Anisotropy and Methods to Form Same
Interposer Design in Package Structures for Wire Bonding Applications
Thin Film Cap to Lower Leakage in Low Band Gap Material Devices
Multi-Conductor Interconnect Structure for a Microelectronic Device
Die Interconnect Substrate, an Electrical Device, and a Method for Forming a Die Interconnect Substrate
Supply Margining Method and Apparatus
Subsystem-Based Soc Integration
Non-Planar Semiconductor Device Having Doped Sub-Fin Region and Method to Fabricate Same
Package Power Delivery Using Plane and Shaped Vias
Method for Fabricating Transistor with Thinned Channel
Dual-Damascene Zero-Misalignment-via Process for Semiconductor Packaging
Techniques for Generating a Routing Table for a Mesh Network Having Ad Hoc Connections
Pci Express Tunneling Over a Multi-Protocol I/O Interconnect
Methods and Systems for Motion Vector Derivation at a Video Decoder
Electromigration Resistant and Profile Consistent Contact Arrays
Apparatus for Low Power Write and Read Operations for Resistive Memory
Controlling Power Delivery To A Processor Via A Bypass
Folding Devices
Decoupled via Fill
Single-Package Wireless Communication Device
High Density Interconnect Device and Method
Stacked Transistor Architecture Having Diverse Fin Geometry
Power Governance of Processing Unit
Avatar Animation System
Scalable Real-Time Face Beautification of Video Images
Intelligent Vehicle Navigator
Temporal Motion Vector Prediction Control in Video Coding
Presenting Advertisements During Media Content Seek
Workload Scheduler for Computing Devices with Camera
Synthesis of Transformed Image Views
Dense Memory Arrays Utilizing Access Transistors with Back-Side Contacts
Array Imaging System Having Discrete Camera Modules and Method for Manufacturing the Same
Polarization Gate Stack Sram
Light Pattern Based Vehicle Location Determination Method and Apparatus
Techniques to Couple High Bandwidth Memory Device on Silicon Substrate and Package Substrate
Platform Power Consumption Reduction via Power State Switching
Interface Engine Providing a Continuous User Interface
Patent:
48,596 →
Application:
16/776,438 →
Methods of Forming Doped Source/Drain Contacts and Structures Formed Thereby
Device Control for Wireless Charging
Non-Volatile Storage for Graphics Hardware
Methods of Forming a Package Substrate
Non-Planar Semiconductor Device Having Doped Sub-Fin Region and Method to Fabricate Same
Logic Chip Including Embedded Magnetic Tunnel Junctions
Application:
16/831,658 →
Publication:
US 2020/0227472
Secure Memory Repartitioning Technologies
Isolation Well Doping with Solid-State Diffusion Sources for Finfet Architectures
Package-Embedded Thin-Film Capacitors, Package-Integral Magnetic Inductors, and Methods of Assembling Same
Access Network Discovery and Selection
Dynamic Sleep for a Display Panel
Interlayer Dielectric for Non-Planar Transistors
Cobalt Based Interconnects and Methods of Fabrication Thereof
Vehicular Occupancy Assessment
Application:
16/897,965 →
Publication:
US 2020/0298730
Intelligent Vehicle Point of Focus Communication
Methods and Apparatus for Battery Current Monitoring
Dielectric and Isolation Lower Fin Material for Fin-Based Electronics
Prepackaged Stair-Stacked Memory Module in a Chip Scale System in Package, and Methods of Making Same
Single-Package Wireless Communication Device
Technologies for Providing Information to a User While Traveling
Systems and Method for Selling Content Over a Network
Mobile Augmented Reality System
Streaming On Diverse Transports
Techniques for Multi-Read and Multi-Write of Memory Circuit
Methods and Arrangements for Vehicle-to-Vehicle Communications
Stair-Stacked Dice Device in a System in Package, and Methods of Making Same
Generation of Synthetic 3-Dimensional Object Images for Recognition Systems
Integrated Circuit Devices with Non-Collapsed Fins and Methods of Treating the Fins to Prevent Fin Collapse
Application:
17/032,063 →
Publication:
US 2021/0013199
Integrated Circuit Devices with Non-Collapsed Fins and Methods of Treating the Fins to Prevent Fin Collapse
Polarization Gate Stack Sram
Electronic Device Including a Lateral Trace
Electromigration Resistant and Profile Consistent Contact Arrays
Subtractive Plug and Tab Patterning with Photobuckets for Back End of Line (Beol) Spacer-Based Interconnects
Optimizing Power Usage by Factoring Processor Architectural Events to Pmu
Application:
17/097,325 →
Publication:
US 2021/0064117
Internet of Things Battery Device
Methods and Systems for Motion Vector Derivation at a Video Decoder
Distribution of Tasks Among Asymmetric Processing Elements
Content Adaptive Quantization for Video Coding
Process-Based Multi-Key Total Memory Encryption
Inferred Undocking for Hybrid Tablet Computer
Application:
17/147,288 →
Publication:
US 2021/0132658
Method for Fabricating Transistor with Thinned Channel
Apparatus and Method for Conservative Morphological Antialiasing with Multisampling
Interposer Design in Package Structures for Wire Bonding Applications
Non-Planar Semiconductor Device Having Doped Sub-Fin Region and Method to Fabricate Same
Method for Orienting Solder Balls on a Bga Device
Semiconductor Packaging with High Density Interconnects
Package-Level Noise Filtering for Emi Rfi Mitigation
Folding Devices
Microelectronic Devices Having Air Gap Structures Integrated with Interconnect for Reduced Parasitic Capacitances
Processor Having Accelerated User Responsiveness In Constrained Environment
Digital Advertising System
Application:
17/222,102 →
Publication:
US 2021/0326931
Bidirectional Power Management Techniques
Platform and Processor Power Management
Finfet Transistor Having a Doped Subfin Structure to Reduce Channel to Substrate Leakage
Systems and Methods for Selling Content Over a Network
Application:
17/359,256 →
Publication:
US 2021/0319419
Techniques to Couple High Bandwidth Memory Device on Silicon Substrate and Package Substrate
Method, System, and Device for Selecting and Displaying Information on a Mobile Digital Display Device
Application:
17/377,085 →
Publication:
US 2021/0342112
Face Augmentation in Video
Techniques for Command Validation for Access to a Storage Device by a Remote Client
Controlling Power Delivery To A Processor Via A Bypass
Power Governance of Processing Unit
Intelligent Vehicle Navigator
Aggregated Analytics for Intelligent Transportation Systems
Dielectric and Isolation Lower Fin Material for Fin-Based Electronics
High Density Interconnect Device and Method
Self-Aligned 3-D Epitaxial Structures for Mos Device Fabrication
Designs and Methods for Conductive Bumps
Application:
17/519,468 →
Publication:
US 2022/0059484
Streaming On Diverse Transports
Non-Planar Semiconductor Device Having Omega-Fin with Doped Sub-Fin Region and Method to Fabricate Same
Application:
17/569,376 →
Publication:
US 2022/0130962
Textile Patterning for Subtractively-Patterned Self-Aligned Interconnects, Plugs, and Vias
Selectively Augmenting Communications Transmitted by a Communication Device
Electromigration Resistant and Profile Consistent Contact Arrays
Cobalt Based Interconnects and Methods of Fabrication Thereof
Method of Forming High Density, High Shorting Margin, and Low Capacitance Interconnects by Alternating Recessed Trenches
Array Imaging System Having Discrete Camera Modules and Method for Manufacturing the Same
Mobile Augmented Reality System
Application:
17/866,380 →
Publication:
US 2022/0351473
Light Pattern Based Vehicle Location Determination Method and Apparatus
Content Adaptive Quantization for Video Coding
Platform Power Consumption Reduction via Power State Switching
Electronic Display Device
Patent:
735,717 →
Application:
29/441,013 →
Electronic Device with a Modular Tablet Stand
Patent:
783,625 →
Application:
29/513,136 →
Electronic Device
Patent:
766,233 →
Application:
29/535,050 →
Electronic Device with a Modular Tablet Stand
Patent:
824,914 →
Application:
29/592,421 →
Electronic Device with a Modular Tablet Stand
Patent:
848,442 →
Application:
29/592,438 →
Electronic Device with a Modular Tablet Stand
Patent:
917,494 →
Application:
29/659,101 →
Electronic Device with a Tablet Stand
Patent:
997,947 →
Application:
29/780,701 →
Priority-based transmission in IEEE 802.11 networks
Application:
60/307,542 →
Asynchronous crossbar circuit with deterministic or arbitrated control
Application:
60/352,131 →
Real-time distribution of dynamic maps
Application:
60/377,019 →
Large capacity switching system
Application:
60/387,394 →
Variable impedance output driver architecture
Application:
60/447,132 →
System and method for uninterrupted streaming
Application:
60/451,975 →
Additive digital predistortion using the CORDIC algorithm
Application:
60/463,228 →
RF amplifier employing active load linearization
Application:
60/468,309 →
Egocentric spatial data model for intelligent mobile geographic information systems
Application:
60/523,581 →
Digital predistortion system and method for high efficiency transmitters
Application:
60/549,789 →
Method and apparatus for providing information services relevant to visual imagery
Application:
60/606,282 →
Shared-memory switch fabric architecture
Application:
60/643,794 →
Apparatuses for communicating within a wireless network using two frequency bands
Application:
60/730,574 →
Dual staggered vertically polarized variable azimuth beam width antenna for wireless network
Application:
60/906,161 →
Power management of low power link states
Application:
60/930,247 →
Antenna Training and Tracking Protocol (ATTP)
Application:
60/969,505 →
Buffering Techniques for Power Management
Application:
60/973,031 →
Techniques for Communications Based Power Management
Application:
60/973,035 →
Techniques for Communications Power Management Based on System States
Application:
60/973,038 →
Techniques for Collaborative Power Management for Heterogeneous Networks
Application:
60/973,044 →
Interactive Fitness Training Program
Application:
61/058,173 →
Distribution of tasks among asymmetric processing elements
Application:
61/067,737 →
Method and System for Gesture Recognition
Application:
61/153,229 →
Method and Apparatus to Estimate Motion Based on Reconstructed Reference Frames at a Video Decoder
Application:
61/222,982 →
Methods and Systems to Derive a Motion Vector at a Video Decoder
Application:
61/222,984 →
Adaptive Clock Recovery
Application:
61/292,534 →
Cluster Enhancement for P2P
Application:
61/304,974 →
Platform energy harvesting
Application:
61/335,153 →
System and Method for Video Stabilization to a Global 3D Frame of Reference by Fusing Orientation Sensor and Image Alignment Data
Application:
61/353,982 →
Dispersed Access Load Over Time
Application:
61/388,430 →
Automated Privacy Adjustments to Video Conferencing Streams
Application:
61/494,034 →
Apparatus, Systems and Methods for Wireless Charging for Pc Platforms and Peripherals
Application:
61/499,600 →
Digital Home User Interface and Remote Controls
Application:
61/508,375 →
Methods and Techniques for Improving Hidden Node Problem in a Wireless System
Application:
61/562,184 →
Techniques for Remote Storage Using Circuitry
Application:
61/587,541 →
Efficiency of Wireless Wide Area Networks Utilizing Local Wireless Connections
Application:
61/621,395 →
Interference Mitigation in Heterogeneous Networks
Application:
61/648,426 →
Methods and Arrangements to Establish an Application Session Based Secure Peer-to-Peer Link
Application:
61/680,695 →
Method, Apparatus and System to Increase Time for Beamforming Report in a Wireless Network
Application:
61/682,054 →
Preventing Unauthorized Access to Audio Video Streams
Application:
61/697,497 →
Frequency Selection Granularity for Integrated Circuits
Application:
61/699,982 →
Methods, Systems and Apparatuses for Frequency Selective Transmission
Application:
61/710,400 →
Methods and Arrangements for Frequency Selective Transmission
Application:
61/716,481 →
Retractable Displays for Helmets
Application:
61/724,962 →
Apparatus, System and Method of Controlling Data Flow Over a Wireless Communication Link
Application:
61/729,368 →
Memory Per Bit Voltage Reference
Application:
61/731,906 →
Memory Refresh Management
Application:
61/748,924 →
Method of Signaling Synchronization Frame Transmission Request
Application:
61/756,548 →
Method and Apparatus to Optimize Command Timing to Dynamic Random Access Memory Based on Memory Error Detection
Application:
61/758,482 →
Moving Stills
Application:
61/766,827 →
Multiport Memory Cell Having Improved Density Area
Application:
61/800,885 →
Timing Control for Unmatched Signal Receiver
Application:
61/841,857 →
Techniques Allowing Physical Sensing in Wireless Charging to Reduce Standby Power
Application:
61/856,219 →
Adaptive Learning Environment Driven by Real Time Identification of Learner States
Application:
61/887,766 →
RATE ADAPTATION IN FULL DUPLEX WIRELESS LANs
Application:
61/911,074 →
Systems and Techniques for User Interface Control
Application:
61/923,595 →
Assistance Information for Enb Parameters Tuning in Lte Systems
Application:
61/933,877 →
Method for Fast and Efficient Mmwave Capable Small Cell Detection
Application:
61/934,525 →
Embedded Universal Serial Bus Solutions
Application:
61/937,878 →
Method and Apparatus for Bluetooth-Based General Service Discovery
Application:
61/988,827 →
User Interaction with Wearable Devices
Application:
62/010,405 →
Adaptive Discovery Window for Fine Timing Measurement
Application:
62/010,667 →
Systems, Methods, and Devices for Social Proximity FTMR Multicast Signaling
Application:
62/025,890 →
Camera Calibration
Application:
62/046,788 →
Apparatus, System and Method of Peer to Peer Communication
Application:
62/072,649 →
Facial Spoofing Detection in Image Based Biometrics
Application:
62/079,020 →
Screen Reflection Anti-Spoofing System and Method
Application:
62/079,082 →
Underlying Absorbing or Conducting Layer for Ebeam Direct Write (Ebdw) Lithography
Application:
62/103,459 →
Simulating Multi-Camera Imaging Systems
Application:
62/116,625 →
ENHANCEMENTS TO PROXIMITY SERVICES (ProSe) PROTOCOLS FOR V2X COMMUNICATIONS IN LTE/5G
Application:
62/184,156 →
Performance of Additional Refresh Operations During Self-Refresh Mode
Application:
62/265,054 →
Hand Gesture Recognition for Cursor Control
Application:
62/275,057 →
Motion Sensor Co-Located with RFID Reader/ Probabilistic Inventory Application for RFID Reader
Application:
62/300,637 →
Substrate-Free Wafer Level System in Package Design Using Silicon Interposer and Wafer Level Through Mold via Process
Application:
62/313,490 →
Autonomous Algorithms to Control a Network of RFID Readers for Optimized Asset Tracking and Inventory Management
Application:
62/369,488 →
System for Improved Power Distribution Through Dimm Voltage Sense Feedback
Application:
62/462,944 →
Integrated Error Checking and Correction (Ecc) in Byte Mode Memory Devices
Application:
62/465,837 →
Apparatus, System and Method of Communicating Over a Media Agnostic (Ma) Usb Connection
Application:
62/558,501 →
Streaming On Diverse Transports
Application:
62/579,107 →
Scalable Multi-Key Encryption Within the Coherency Domain of a Processor
Application:
62/678,783 →
Related Assignments
(3)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Interest
May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Assignment of Assignor's Interest
Jan 19, 2017
From: TEXAS INSTRUMENTS INCORPORATED
To: INTEL CORPORATION
Reel/Frame 041383/0040 →
Corrective Assignment to Correct the Replace Erroneously Filed Patent #7358718 with the Correct Patent #7358178 Previously Recorded on Reel 038669 Frame 0001. Assignor(S) Hereby Confirms the Security Interest.
Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →