Instruction-set architecture for programmable cyclic redundancy check (CRC) computations

1. A processor comprising:

an execution unit to perform a sequence of operations for a Cyclic Redundancy Check (CRC) instruction that identifies a first operand and a second operand, the sequence of operations to perform a CRC operation on a 2n-bit data block of the second operand using one of a plurality of different n-bit polynomials of the first operand to cause the execution unit to:

expand an n-bit polynomial to provide a pre-computed polynomial K; and

perform a sequence of micro-operations on the 2n-bit data block using the n-bit polynomial, a current n-bit residue of the first operand and the pre-computed polynomial K to provide an n-bit residue for the 2n-bit data block, including a shuffle by selection of an n-bit portion from the first operand and an n-bit portion from the second operand to store in a destination location.

2. The processor of claim 1 , wherein the n-bit polynomial has a maximal degree of n+1.

3. The processor of claim 1 , wherein the first operand has 2n-bits and the second operand has 2n-bits.

4. The processor of claim 3 , wherein n is 32.

5. The processor of claim 1 , wherein the first operand is both a source and a destination and the n-bit residue is stored in the first operand.

6. The processor of claim 1 , wherein the execution unit is to perform a shuffle word micro-instruction to shuffle bits within the respective n-bit portions.

7. The processor of claim 1 , wherein the sequence of micro-operations comprises:

a CRC reduction micro-instruction to reduce an n+8-bit data using the pre-computed polynomial K to provide an n+4-bit intermediate residue and to reduce the n+4 intermediate residue to an n-bit residue using the n-bit polynomial.

8. A machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:

performing a sequence of operations for a Cyclic Redundancy Check (CRC) instruction, the CRC instruction having a first operand and a second operand, the sequence of operations to perform a Cyclic Redundancy Check (CRC) operation on a 2n-bit data block stored in the second operand using one of a plurality of different n-bit polynomials stored in the first operand, comprising:

expanding an n-bit polynomial to provide a pre-computed polynomial K; and

performing a sequence of micro-operations on the 2n-bit data block using the n-bit polynomial and current n-bit residue stored in the first operand and the pre-computed polynomial K to provide an n-bit residue for the 2n-bit data block, wherein performing the sequence of micro-operations comprises reducing an n+8-bit data using the pre-computed polynomial K to provide an n+4-bit intermediate residue and to reduce the n+4 intermediate residue to an n-bit residue using the n-bit polynomial.

9. The machine-readable medium of claim 8 , wherein the n-bit polynomial has a maximal degree of n+1.

10. The machine-readable medium of claim 9 , wherein the first operand has 2n-bits and the second operand has 2n-bits.

11. The machine-readable medium of claim 10 , wherein n is 32.

12. The machine-readable medium of claim 9 , wherein the first operand is both a source and a destination and the n-bit residue is stored in the first operand.

13. The machine-readable medium of claim 9 , wherein performing the sequence of micro-operations comprises:

performing a shuffle by selecting an n-bit portion from the first operand and an n-bit portion from the second operand to store in a 2n-bit destination operand.

14. The machine-readable medium of claim 13 , wherein the method further comprises performing the shuffle to shuffle bits within the respective n-bit portions.

15. A system comprising:

a processor including:

an execution unit to execute a Cyclic Redundancy Check (CRC) instruction, the CRC instruction to identify a first operand and a second operand, wherein the execution unit is to perform a CRC operation on a 2n-bit data block stored in the second operand using one of a plurality of different n-bit polynomials of the first operand to cause the execution unit to:

expand an n-bit polynomial to provide a pre-computed polynomial K; and

perform a sequence on the 2n-bit data block using the n-bit polynomial, a current n-bit residue of the first operand and the pre-computed polynomial K to provide an n-bit residue for the 2n-bit data block, wherein the sequence is to reduce an x-bit data using the pre-computed polynomial K to provide a y-bit intermediate residue and reduce the y-bit intermediate residue to an n-bit residue using the n-bit polynomial; and

a dynamic random access memory coupled to the processor.

16. The system of claim 15 , wherein the processor comprises a fetch unit to fetch instructions.

17. The system of claim 16 , wherein the processor further comprises a decode unit to decode fetched instructions.

18. The system of claim 17 , wherein the processor further comprises a register file including a plurality of registers.

19. The system of claim 17 , wherein the processor further comprises a retirement unit to retire executed instructions.

20. The system of claim 19 , wherein the processor further comprises a cache coupled to the execution unit and the retirement unit.