Strain inducing semiconductor regions
View Patent ↗A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.
1. A semiconductor device comprising:
a substrate having a strained channel region; and
crystalline source- and drain (S/D) regions directly adjacent the strained channel region, wherein the strained channel region includes Si x Ge 1-x and the crystalline S/D regions includes Si y Ge 1-y , where 0<x<1, x≠y, and 0<y<1, and wherein the Si x Ge 1-x is directly adjacent to the Si y Ge 1-y .
2. The semiconductor device of claim 1 , wherein S/D regions further include tip extensions that are also directly adjacent the strained channel region.
3. The semiconductor device of claim 1 , wherein the substrate imparts a uniaxial strain to the strained channel region.
4. The semiconductor device of claim 1 , wherein the substrate imparts a uniaxial tensile strain to the strained channel region.
5. The semiconductor device of claim 1 , wherein the substrate imparts a uniaxial compressive strain to the strained channel region.
6. The semiconductor device of claim 1 , wherein the lattice constant of the crystalline S/D regions is different from the lattice constant of strained channel region by a factor of at least 0.1%.
7. The semiconductor device of claim 1 wherein the strained channel region is contained in a quantum well region.
8. The semiconductor device of claim 1 , wherein strained channel region has a rectilinear boundary with at least one of the crystalline S/D regions.
9. A semiconductor device comprising:
a raised, 3-dimensional strained channel region disposed above a substrate; and
a raised epitaxial source-and drain (S/D) regions disposed directly adjacent the raised, 3-dimensional strained channel region and also disposed above the substrate, wherein the raised, 3-dimensional strained channel region includes Si x Ge 1-x and the raised epitaxial S/D regions includes Si y Ge 1-y , where 0<x<1, x≠y, and 0<y<1, and wherein the Si x Ge 1-x is directly adjacent to the Si y Ge 1-y .
10. The semiconductor device of claim 9 , wherein the raised epitaxial S/D regions impart a uniaxial strain to the raised, 3-dimensional strained channel region.
11. The semiconductor device of claim 9 , wherein the raised epitaxial S/D regions impart a uniaxial tensile strain to the raised, 3-dimensional strained channel region.
12. The semiconductor device of claim 9 , wherein the raised epitaxial S/D regions impart a uniaxial compressive strain to the raised, 3-dimensional strained channel region.
13. The semiconductor device of claim 9 , wherein the lattice constant of the raised epitaxial S/D regions is different from the lattice constant of the raised, 3-dimensional strained channel region by a factor of at least 0.1%.
14. The semiconductor device of claim 9 wherein the raised, 3-dimensional strained channel region is contained in a quantum well region.
15. The semiconductor device of claim 9 , wherein the raised, 3-dimensional strained channel region has a rectilinear boundary with at least one of the raised epitaxial S/D regions.