Method and apparatus to process 4-operand SIMD integer multiply-accumulate instruction
View Patent ↗According to one embodiment, a processor includes an instruction decoder to receive an instruction to process a multiply-accumulate operation, the instruction having a first operand, a second operand, a third operand, and a fourth operand. The first operand is to specify a first storage location to store an accumulated value; the second operand is to specify a second storage location to store a first value and a second value; and the third operand is to specify a third storage location to store a third value. The processor further includes an execution unit coupled to the instruction decoder to perform the multiply-accumulate operation to multiply the first value with the second value to generate a multiply result and to accumulate the multiply result and at least a portion of a third value to an accumulated value based on the fourth operand.
1. A processor, comprising:
an instruction decoder to receive an instruction to process a multiply-accumulate operation, the instruction having a first operand, a second operand, a third operand, and a fourth operand, the first operand to specify a first storage location to store an accumulated value, the second operand to specify a second storage location to store a first value and a second value, the third operand to specify a third storage location to store a third value; and
an execution unit coupled to the instruction decoder to perform the multiply-accumulate operation to multiply the first value with the second value to generate a multiply result and to accumulate the multiply result and at least a portion of the third value to the accumulated value based on the fourth operand, wherein the fourth operand to store a value indicating the at least a portion of the third value to be added to the accumulated value.
2. The processor of claim 1 , wherein a result of the multiply-accumulate operation is stored in the first storage location indicated by the first operand.
3. The processor of claim 1 , wherein a higher portion of the third value is accumulated when the value of the fourth storage location contains a first value, and wherein a lower portion of the third value is accumulated when the value of the fourth storage location contains a second value.
4. The processor of claim 1 , wherein the first, second, and third operands have at least 512 bits, and wherein the execution unit is to perform at least four iterations of the multiply-accumulate operation, each iteration occupying at least 128 bits.
5. The processor of claim 1 , wherein for a current iteration of multiply-accumulate operations, a multiplication is performed between the (i+63:i) bits of the second operand and the (i+127:i+64) bits of the second operand, a first addition is performed between the multiplication and the (i+63:i) bits of the first operand, and a second addition is performed between the first addition and the (i+63:i) bits of the third operand as specified by the fourth operand.
6. The processor of claim 5 , wherein a third addition is performed between a first set of carry bits resulting from the first addition and a second set of carry bits resulting from the second addition.
7. The processor of claim 5 , wherein the second addition is performed between the first addition and the (i+127:i+64) bits of the third operand as specified by the fourth operand.
8. A method, comprising:
receiving, by an instruction decoder of a processor, an instruction having a first operand, a second operand, a third operand, and fourth operand, the first operand to specify a first storage location to store an accumulated value, the second operand to specify a second storage location to store a first value and a second value, the third operand to specify a third storage location to store a third value; and
performing, by an execution unit of the processor, a multiply-accumulate operation to multiply the first value with the second value to generate a multiply result and to accumulate the multiply result and at least a portion of the third value to an accumulated value based on the fourth operand, wherein the fourth operand to store a value indicating the at least a portion of the third value to be added to the accumulated value.
9. The method of claim 8 , wherein a result of the multiply-accumulate operation is stored in the first storage location indicated by the first operand.
10. The method of claim 8 wherein a higher portion of the third value is accumulated when the value of the fourth storage location contains a first value, and wherein a lower portion of the third value is accumulated when the value of the fourth storage location contains a second value.
11. The method of claim 8 , wherein the first, second, and third operands have at least 512 bits, and wherein the execution unit is to perform at least four iterations of the multiply-accumulate operation, each iteration occupying at least 128 bits.
12. The method of claim 8 , wherein for a current iteration of multiply-accumulate operations, a multiplication is performed between the (i+63:i) bits of the second operand and the (i+127:i+64) bits of the second operand, a first addition is performed between the multiplication and the (i+63:i) bits of the first operand, and a second addition is performed between the first addition and the (i+63:i) bits of the third operand as specified by the fourth operand.
13. The method of claim 12 , wherein a third addition is performed between a first set of carry bits resulting from the first addition and a second set of carry bits resulting from the second addition.
14. The method of claim 12 , wherein the second addition is performed between the first addition and the (i+127:i+64) bits of the third operand as specified by the fourth operand.
15. A data processing system, comprising:
an interconnect;
a processor coupled to the interconnect to receive an instruction having a first operand, a second operand, a third operand, and fourth operand, the first operand to specify a first storage location to store an accumulated value, the second operand to specify a second storage location to store a first value and a second value, the third operand to specify a third storage location to store a third value, and the processor to perform a multiply-accumulate operation to multiply the first value with the second value to generate a multiply result and to accumulate the multiply result and at least a portion of the third value to an accumulated value based on the fourth operand, wherein the fourth operand to store a value indicating the at least a portion of the third value to be added to the accumulated value; and
a dynamic random access (DRAM) coupled to the interconnect.
16. The system of claim 15 , wherein a result of the multiply-accumulate operation is stored in the first storage location indicated by the first operand.
17. The system of claim 15 , wherein a higher portion of the third value is accumulated when the value of the fourth storage location contains a first value, and wherein a lower portion of the third value is accumulated when the value of the fourth storage location contains a second value.
18. The system of claim 15 , wherein the first, second, and third operands have at least 512 bits, and wherein the execution unit is to perform at least four iterations of the multiply-accumulate operation, each iteration occupying at least 128 bits.
19. The system of claim 15 , wherein for a current iteration of multiply-accumulate operations, a multiplication is performed between the (i+63:i) bits of the second operand and the (i+127:i+64) bits of the second operand, a first addition is performed between the multiplication and the (i+63:i) bits of the first operand, and a second addition is performed between the first addition and the (i+63:i) bits of the third operand as specified by the fourth operand.
20. The system of claim 19 , wherein a third addition is performed between a first set of carry bits resulting from the first addition and a second set of carry bits resulting from the second addition.
21. The system of claim 19 , wherein the second addition is performed between the first addition and the (i+127:i+64) bits of the third operand as specified by the fourth operand.