Sense amplifier with reduced detection error
View Patent ↗This invention provides a type of sense amplifier, a type of bit line circuit, a type of storage device, and a method for amplifying a read signal characterized by the fact that it has a small detection error of the read signal and has low power consumption. With bit lines (BL, BLZ) and input terminals (SA, SAZ) of the amplifier connected to each other by means of a CMOS switch circuit, as control signal ENN becomes high level, amplification of the read signal in the amplifier starts and, at the same time, the amplified signal is held. After a time delay determined by delay circuit U 1 from the start of amplification of the read signal, control signal GEN 1 and control signal GEN 2 output from said delay circuit U 1 are changed, and connection between the bit line and amplifier is cut off. Consequently, while the small potential difference at the start of amplification is kept by the current from the bit line, the amplification operation is carried out to a certain degree, and then the bit line is cut off from the amplifier. Consequently, a detection error in the read signal can hardly take place.
1. A semiconductor storage device comprising:
an amplifier that is activated corresponding to a control signal and amplifies the potential difference between a first node and a second node;
a first switch circuit that is connected between a first bit line and said first node and is controlled to the OFF state after activation of said amplifier;
a second switch circuit that is connected between a second bit line and said second node and is controlled to the OFF state after activation of said amplifier; and
a delay circuit that outputs said control signal with a prescribed delay time and, by means of an output signal of said delay circuit, said first switch circuit and said second switch circuit are controlled to be OFF.
2. The semiconductor storage device of claim 1 , wherein said first switch circuit and said second switch circuit have a p-type MOS transistor and an n-type MOS transistor coupled together in parallel, and said p-type MOS transistor and n-type MOS transistor are controlled to be OFF at the same time.
3. The semiconductor storage device of claim 1 , wherein said amplifier has a first inverter coupled between said second node and said first node, a second inverter coupled between said first node and said second node, and a switching element that responds to said control signal and couples said first inverter and said second inverter to a power source.
4. The semiconductor storage device of claim 1 , further comprising a first charging circuit which is coupled to said first bit line and said second bit line and which charges said first bit line and said second bit line to a prescribed potential.
5. The semiconductor storage device of claim 4 , further comprising a second charging circuit which is coupled to said first node and said second node and which charges said first node and said second node to a prescribed potential.
6. The semiconductor storage device of claim 5 , wherein the charging operation of said first charging circuit and said second charging circuit comes to an end before activation of said amplifier.
7. The semiconductor storage device of claim 5 , further comprising a first data write circuit coupled to said first bit line and a second data write circuit coupled to said second bit line.