DMA (direct memory access) coalescing
View Patent ↗In general, in one aspect, a method includes determining a repeated, periodic DMA (Direct Memory Access) coalescing interval based, at least in part, on a power sleep state of a host platform. The method also includes buffering data received at the device in a FIFO (First-In-First-Out) queue during the interval and DMA-ing the data enqueued in the FIFO to a memory external to the device after expiration of the repeated, periodic DMA coalescing interval.
1. A method comprising, at a device having at least one Direct Memory Access (DMA) engine:
determining a repeated, periodic DMA coalescing interval based, at least in part, on a time period of a power sleep state of a host platform that is calculated to permit at least a sufficient amount of power consumption savings to result;
buffering data received at the device in a FIFO (First-In-First-Out) queue during the repeated, periodic DMA coalescing interval; and
DMA-ing the data enqueued in the FIFO to a memory external to the device after expiration of the repeated, periodic DMA coalescing interval.
2. The method of claim 1 , wherein the device comprises a network interface controller comprising at least one PHY and at least one MAC (media access controller).
3. The method of claim 1 , further comprising:
disabling DMA coalescing based on a first determined rate of data; and
resuming DMA coalescing based on a second determined rate of data.
4. The method of claim 1 , further comprising:
detecting at least one characteristic of a packet received by the device based on at least one packet header field; and
based on the detecting the at least one characteristic, DMA-ing at least the packet prior to expiration of the repeated, periodic DMA coalescing interval.
5. The method of claim 1 , further comprising:
determining timing of at least one interrupt generated by the device based on the repeated, periodic DMA coalescing interval.
6. The method of claim 5 , wherein the timing of the at least one interrupt comprises a first interrupt based on an end of a first DMA coalescing interval.
7. The method of claim 1 , further comprising:
receiving a signal from a host processor sent to multiple coupled devices; and
in response, terminating the DMA coalescing interval prematurely.
8. The method of claim 1 , wherein the determining comprises repeatedly dynamically adjusting the DMA coalescing interval during continuing operation.
9. The method of claim 1 , further comprising:
comparing buffer occupancy with a threshold; and
based on the comparing, terminating DMA coalescing prior to the expiration of the repeated, periodic DMA coalescing interval.
10. A network interface controller comprising:
at least one PHY;
at least one MAC (media access controller) communicatively coupled to the at least one PHY;
at least at least one Direct Memory Access (DMA) engine to transfer packets received via the at least on PHY and at least one MAC to a host memory;
logic to:
determine a repeated, periodic DMA coalescing interval based, at least in part, on a time period of a power sleep state of a host platform that is calculated to permit at least a sufficient amount of power consumption savings to result;
buffer data received at the device in a FIFO (First-In-First-Out) queue during the repeated, periodic DMA coalescing interval; and
DMA the data enqueued in the FIFO to a memory external to the device after expiration of the repeated, periodic DMA coalescing interval.
11. The network interface controller of claim 10 , further comprising logic to:
disable DMA coalescing based on a first determined rate of data; and
resume DMA coalescing based on a second determined rate of data.
12. The network interface controller of claim 10 , further comprising logic to:
detect at least one characteristic of a packet received by the device based on at least one packet header field; and
based on the detecting the at least one characteristic, DMA at least the packet prior to expiration of the repeated, periodic DMA coalescing interval.
13. The network interface controller of claim 10 , further comprising logic to:
determine timing of at least one interrupt generated by the device based on the repeated, periodic DMA coalescing interval.
14. The network interface controller of claim 13 , wherein the timing of the at least one interrupt comprises a first interrupt based on an end of a first DMA coalescing interval.
15. The network interface controller of claim 10 , further comprising logic to:
receive a signal sent to multiple coupled devices; and
in response, terminating the DMA coalescing interval prematurely.
16. The network interface controller of claim 15 , wherein the logic to determine comprises logic to repeatedly, dynamically adjust the DMA coalescing interval during continuing operation.
17. The network interface controller of claim 10 , further comprising logic to:
compare buffer occupancy with a threshold; and
based on the comparing, terminate DMA coalescing prior to the expiration of the repeated, periodic DMA coalescing interval.