Programming multilevel cell phase change memories
View Patent ↗A multilevel phase change memory cell may have a plurality of intermediate levels between a set and a reset or a crystalline and amorphous states. These intermediate levels between set and reset may be differentiated not only by programming current, but also by different programming pulse widths. As a result, the intermediate states may be positioned, on the programming current versus programming pulse width curve, in regions of common resistance with a relatively large range of programming current.
1. A method comprising:
using a first pulse width and a first programming current level to program a first level of a multilevel phase change memory cell; and
programming said cell to a second level using both of a different pulse width and a different programming current.
2. The method of claim 1 including using different programming currents and different pulse widths to program a multilevel cell.
3. The method of claim 1 including selecting a resistance band for a particular level of a multilevel cell.
4. The method of claim 2 including selecting resistance band with a larger range of programming current.
5. A phase change memory comprising:
an array of multilevel phase change memory cells, one of said cells including an ovonic unified memory and an ovonic threshold switch; and
a controller to program a cell using different pulse widths.
6. The memory of claim 5 including using different programming currents to program one of said cells.
7. The memory of claim 5 , one of said cells including at least two levels, said controller to use different pulse widths to program the two levels.
8. The memory of claim 5 , said controller to apply current pulses to program one of said cells.
9. The memory of claim 5 , said controller to program at least three different levels by changing the pulse width of a programming pulse.
10. The system of claim 7 , said controller to program at least three different levels by changing the pulse width of a programming pulse.
11. A system comprising:
a processor; and
a multilevel phase change memory programmable using a first pulse width in a first programming current level to program a first level of a multilevel phase change memory cell and to program a second level using both of a different pulse width and a different programming current.
12. The system of claim 11 wherein said cell is programmable using different current amplitudes.
13. The system of claim 11 , said memory including a controller.
14. The system of claim 13 , said cell having at least two levels, said controller to use different pulse widths to program the two levels.