APPLICATION SCHEDULING IN HETEROGENEOUS MULTIPROCESSOR COMPUTING PLATFORMS
Methods and apparatus to schedule applications in heterogeneous multiprocessor computing platforms are described. In one embodiment, information regarding performance (e.g., execution performance and/or power consumption performance) of a plurality of processor cores of a processor is stored (and tracked) in counters and/or tables. Logic in the processor determines which processor core should execute an application based on the stored information. Other embodiments are also claimed and disclosed.
1 . A processor comprising:
a storage unit to store information corresponding to performance of a plurality of processor cores of the processor, wherein the plurality of processor cores are heterogeneous; and
logic to determine a first processor core, of the plurality of processor cores, to execute an application, using performance-based core modeling prediction heuristics based on the stored information, and to cause scheduling of the application for execution on the first processor core.
2 . The processor of claim 1 , wherein the logic is to transmit data to the operating system to cause scheduling of the application on the first processor core in response to detection of a context switch.
3 . The processor of claim 2 , wherein the logic is to update the stored information based on collected information.
4 . The processor of claim 3 , wherein the storage unit is to store one or more performance counters.
5 . The processor of claim 4 , wherein the one or more performance counters are to comprise: core clock cycles, instructions retired, level 2 cache misses, scheduler stalls, resource stalls, or branch stalls.
6 . The processor of claim 2 , wherein the logic is to predict execution or power consumption performance of the application on at least some of the plurality of processor cores.
7 . The processor of claim 1 , wherein the storage unit comprises a shared memory, a private cache, a shared cache, or a dedicated memory.
8 . The processor of claim 1 , wherein the stored information is stored in a process control block of the application.
9 . The processor of claim 1 , wherein the storage unit is to store a performance history table (PHT).
10 . The processor of claim 8 , wherein each entry in the PHT is to at least store a process identifier and a plurality cycles per instruction corresponding to the plurality of processor cores.