PCI express tunneling over a multi-protocol I/O interconnect
View Patent ↗Described are embodiments of methods, apparatuses, and systems for PCIe tunneling across a multi-protocol I/O interconnect of a computer apparatus. A method for PCIe tunneling across the multi-protocol I/O interconnect may include establishing a first communication path between ports of a switching fabric of a multi-protocol I/O interconnect of a computer apparatus in response to a peripheral component interconnect express (PCIe) device being connected to the computer apparatus, and establishing a second communication path between the switching fabric and a PCIe controller. The method may further include routing, by the multi-protocol I/O interconnect, PCIe protocol packets of the PCIe device from the PCIe device to the PCIe controller over the first and second communication paths. Other embodiments may be described and claimed.
1. A multi-protocol input-output (I/O) interconnect comprising:
a first port; and
a peripheral component interconnect express (PCIe) device associated with the first port of the multi-protocol I/O interconnect, wherein the PCIe device includes:
a PCIe adapter having logic to establish a PCIe virtual link between the first port and a second port, using a multi-protocol I/O interconnect path between the first and second ports, wherein the PCIe adapter is to indicate a bandwidth associated with the interconnect path to the PCIe device.
2. The multi-protocol I/O interconnect of claim 1 , wherein the multi-protocol I/O interconnect is associated with a computing apparatus.
3. The multi-protocol I/O interconnect of claim 1 , wherein the PCIe device is operable with a transport layer to provide indication to the PCIe adapter that the multi-protocol I/O interconnect path between the first and second ports is established.
4. The multi-protocol I/O interconnect of claim 3 , wherein the PCIe adapter is to indicate to the PCIe device that the bandwidth associated with the interconnect path has been changed, wherein the transport layer is to modify the path bandwidth in response to the indication.
5. The multi-protocol I/O interconnect of claim 1 , wherein the PCIe adapter is to indicate to the PCIe device that a virtual link training is to be initiated.
6. The multi-protocol I/O interconnect of claim 5 , wherein the PCIe device further includes a PCIe physical layer logical block to initiate the virtual link training in response to the indication from the PCIe adapter.
7. The multi-protocol I/O interconnect of claim 6 , wherein the PCIe device is operable with a PCIe transaction layer and PCIe data link layer.
8. The multi-protocol I/O interconnect of claim 7 , wherein the PCIe device is to form a multi-protocol interconnect packet to be transmitted via the PCIe virtual link from the first port to the second port.
9. The multi-protocol I/O interconnect of claim 8 , wherein the multi-protocol interconnect packet includes a packet header having a protocol defined field (PDF) to indicate maintenance of synchronization between the PCIe adapter and another PCIe adapter associated with the second port.
10. A method, comprising:
receiving, by a peripheral component interconnect express (PCIe) device associated with a first port of a multi-protocol I/O interconnect of a computing apparatus, an indication that a multi-protocol I/O interconnect path between the first port of the multi-protocol I/O interconnect and a second port is established;
initiating, by the PCIe device, a training of a PCIe virtual link in response to receiving the indication, based on the established multi-protocol I/O interconnect path, including forming a multi-protocol interconnect packet to be transmitted via the PCIe virtual link from the first port to the second port, wherein the multi-protocol interconnect packet includes a packet header that indicates maintenance of synchronization between the first and second ports; and
establishing, by the PCIe device, the PCIe virtual link, based on a result of the training.
11. A computer system, comprising:
a processor;
a memory coupled with the processor; and
a multi-protocol input-output (I/O) interconnect coupled with the processor and memory that includes:
a first port; and
a peripheral component interconnect express (PCIe) device associated with the first port of the multi-protocol I/O interconnect, wherein the PCIe device includes a PCIe adapter having logic to establish a PCIe virtual link between the first port and a second port, using a multi-protocol I/O interconnect path between the first and second ports, wherein the PCIe adapter logic is to indicate a bandwidth associated with the interconnect path to the PCIe device.
12. The computer system of claim 11 , wherein the multi-protocol I/O interconnect is associated with a computing apparatus.
13. The computer system of claim 11 , wherein the PCIe device is operable with a transport layer to provide indication to the PCIe adapter that the multi-protocol I/O interconnect path between the first and second ports is established.
14. The computer system of claim 11 , wherein the PCIe adapter logic is to indicate to the PCIe device that a virtual link training is to be initiated.
15. The computer system of claim 14 , wherein the PCIe device is operable with a PCIe physical layer logical block to initiate the virtual link training in response to the indication from the PCIe adapter.
16. The computer system of claim 15 , wherein the PCIe device is operable with a PCIe transaction layer and PCIe data link layer.
17. The computer system of claim 15 , wherein the PCIe device is to form a multi-protocol interconnect packet to be transmitted via the PCIe virtual link from the first port to the second port.