Apparatus and method for selectively using a memory command clock as a reference clock
View Patent ↗Described herein are embodiments of selectively setting a memory command clock as a memory buffer reference clock. An apparatus configured for setting a memory command clock as a memory buffer reference clock may include a memory buffer configured to interface between a host and memory, and reference clock selection logic configured to selectively set a memory command clock as a memory buffer reference clock. Other embodiments may be described and/or claimed.
1. An apparatus comprising:
a memory buffer configured to interface between a host and memory; and
reference clock selection logic coupled with the memory buffer and configured to selectively set a memory command clock as a memory buffer reference clock for the memory buffer, wherein the reference clock selection logic includes a multiplexer having inputs configured to receive a system reference clock and the memory command clock and an output configured to selectively output the memory command clock as the memory buffer reference clock.
2. The apparatus of claim 1 , wherein the reference clock selection logic is configured to selectively set the memory command clock as the memory buffer reference clock as part of memory link training of the apparatus.
3. The apparatus of claim 1 , wherein the multiplexer is configured to receive the system reference clock from a system clock and the memory command clock from a host.
4. The apparatus of claim 1 , wherein the reference clock selection logic includes a phase-locked loop (PLL) coupled to the output of the multiplexer.
5. The apparatus of claim 4 , wherein the reference clock selection logic is configured to cause the multiplexer to output the system reference clock if the PLL fails to lock the memory command clock.
6. The apparatus of claim 1 , wherein the reference clock selection logic includes a reference clock selection state machine configured to provide a reference clock selection signal to the multiplexer, and wherein the multiplexer is configured to selectively output the memory command clock in response to the reference clock selection signal.
7. The apparatus of claim 6 , wherein the reference clock selection logic includes a phase-locked loop (PLL) coupled to the output of the multiplexer, and wherein the reference clock selection state machine is configured to provide another reference clock selection signal to the multiplexer if the PLL fails to lock the memory command clock.
8. The apparatus of claim 1 , wherein the reference clock selection logic includes a clock divider to receive the memory command clock and to generate one or more other clocks from the memory buffer reference clock.
9. The apparatus of claim 1 , wherein the memory comprises a plurality of double data rate (DDR) memory modules.
10. The apparatus of claim 9 , wherein the plurality of DDR memory modules comprise a plurality of DDR dynamic random access memory modules.
11. The apparatus of claim 1 , wherein the reference clock selection logic is integrated into the memory buffer.
12. A system comprising:
a host;
a plurality of double data rate (DDR) memory modules;
a memory buffer configured to couple the host with the plurality of DDR memory modules;
reference clock selection logic configured to couple the memory buffer and the host, and to selectively set a memory command clock as a memory buffer reference clock for the memory buffer, wherein the reference clock selection logic includes a multiplexer having inputs configured to receive the memory command clock from the host and a system reference clock from an oscillator, and an output configured to selectively output the memory command clock; and
a display device coupled to the host.
13. The system of claim 12 , wherein the reference clock selection logic is configured to selectively set the memory command clock as the memory buffer reference clock as part of memory link training.
14. The system of claim 12 , wherein the reference clock selection logic includes a phase-locked loop (PLL) coupled to the output of the multiplexer.
15. The system of claim 14 , wherein the reference clock selection logic is configured to cause the multiplexer to output the system reference clock if the PLL fails to lock the memory command clock.
16. The system of claim 14 , wherein the reference clock selection logic includes a reference clock selection state machine configured to provide a reference clock selection signal to the multiplexer, and wherein the multiplexer is configured to selectively output the memory command clock in response to the reference clock selection signal.
17. The system of claim 12 , wherein the reference clock selection logic is integrated into the memory buffer.
18. The system of claim 12 , further comprising a network interface coupled with the host, and configured to communicatively couple the system with a network.
19. The system of claim 12 , wherein the system is a selected one of a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant, an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
20. The system of claim 12 , wherein the display device is a touch screen display.
21. The system of claim 12 , wherein the host includes one or more processors.
22. A method comprising:
receiving, by a memory buffer interfacing a host and memory, a system reference clock and a memory command clock;
selectively setting the memory command clock as the memory buffer reference clock;
providing the memory command clock to a phase-lock loop; and
selectively setting the system reference clock as the memory buffer reference clock if the phase-lock loop fails to lock the memory command clock.
23. The method of claim 22 , further comprising performing memory link training to establish one or more links between the host and the memory, and wherein the selectively setting the memory command clock as the memory buffer reference clock is performed during the memory link training.
24. The method of claim 22 , wherein the receiving the system reference clock comprises receiving the system reference clock by the memory buffer from a system clock, and wherein the receiving the memory command clock comprises receiving the memory command clock by the memory buffer from the host.
25. The method of claim 22 , further comprising, after selectively setting the memory command clock as the memory buffer reference clock, generating one or more other clocks from the memory command clock.
26. A non-transitory machine-readable medium having associated instructions that, when executed by an apparatus, cause the apparatus to perform a method comprising:
providing to a memory buffer interfacing a host and memory, a system reference clock and a memory command clock;
selectively setting the memory command clock as the memory buffer reference clock;
providing the memory command clock to a phase-lock loop; and
selectively setting the system reference clock as the memory buffer reference clock if the phase-lock loop fails to lock the memory command clock.
27. The non-transitory machine-readable medium of claim 26 , wherein the operations further include initializing memory link training to establish one or more links between the host and the memory, and wherein the selectively setting the memory command clock as the memory buffer reference clock is performed during the memory link training.