Phase change memory with bipolar junction transistor select device
View Patent ↗A phase change memory may be organized with a global word line coupled to a plurality of blocks, each with a plurality of phase change memory cells arranged in rows and columns. Thus, one global word line may be common to a plurality of blocks. The global word line may be coupled to a word line decoder that is responsible for pulling the word line to ground. Each of the blocks, on the other hand, is coupled to a bitline selector through a bitline. Each block may have its own local word line coupled to the global word line. In some cases, this architecture reduces the minimum capacity of the memory.
1. A method comprising:
providing a phase change memory including a plurality of cells including a phase change memory element and a bipolar junction select transistor;
organizing groups of cells into blocks and providing a plurality of blocks with one global word line decoder coupled to the blocks by a global word line, each block having a separate local word line coupled to said global word line;
using said global word line decoder to pull down the global word line to ground; and
providing a different bitline selector for each block.
2. The method of claim 1 including coupling each block by a bitline to a bitline selector, each block outputting one tile bandwidth.
3. The method of claim 1 including splitting the data for one address location among a plurality of blocks.
4. The method of claim 1 including outputting, from the bitline selector, a tile bandwidth.
5. A phase change memory comprising:
a plurality of cells, each cell including a memory element and a bipolar junction transistor;
a plurality of blocks of cells;
a global word line;
a global word line decoder coupled to each of said blocks through said global word line, each block including a separate local word line coupled to said global word line, said global word line decoder to pull down the global word line to ground; and
a different bitline selector for each block.
6. The memory of claim 5 including a different bitline coupled to each of said blocks and a bitline selector coupled to said bitlines.
7. The memory of claim 6 wherein each block outputs one tile bandwidth.
8. The memory of claim 5 including said bitline selector to output one tile bandwidth.
9. A processor-based system comprising:
a processor;
a static random access memory coupled to said processor; and
a phase change memory coupled to said processor, said phase change memory including a plurality of cells, each cell including a phase change memory element and a bipolar junction transistor, a plurality of blocks of cells, a global word line, and a global word line decoder coupled to each of said blocks through said global word line, each block including a separate local word line coupled to said global word line, and a different bitline selector for each block.
10. The system of claim 9 including a different bitline coupled to each of said blocks and a bitline selector coupled to said bitlines.
11. The system of claim 10 wherein each block outputs one tile bandwidth.
12. The system of claim 9 , said global word line decoder to pull down the global word line to ground.
13. The system of claim 9 including said bitline selector to output one tile bandwidth.