Memory channel with bit lane fail-over
View Patent ↗Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.
1. An integrated circuit to provide a memory buffer to isolate one or more dynamic random access memory devices (DRAM devices) from a unidirectional differential point-to-point channel, the integrated circuit comprising:
an inbound redrive circuit to receive and redrive signals on an inbound path of the unidirectional differential point-to-point channel, the inbound redrive circuit including, at least in part, two or more bit-lanes for the inbound path of the unidirectional differential point-to-point channel;
an idle pattern generator coupled with the inbound redrive circuit, the idle pattern generator to provide a permuting data pattern if the memory buffer is not sending requested data to a host, wherein the permuting data pattern is generated by a 12-bit linear-feedback shift register (LFSR) with a polynomial of x 12 +x 7 +x 4 +x 3 +1;
an outbound redrive circuit to receive and redrive signals on an outbound path of the unidirectional differential point-to-point channel, the outbound redrive circuit including, at least in part, two or more bit-lanes for the outbound path of the unidirectional differential point-to-point channel; and
double data rate (DDR) memory interface to couple the memory buffer with the one or more DRAM devices, the memory interface to receive data from the outbound redrive circuit and to send data to the inbound redrive circuit.
2. The integrated circuit of claim 1 , wherein the integrated circuit is attached to a printed circuit board (PCB).
3. The integrated circuit of claim 2 , wherein at least on DRAM device is attached to the PCB.
4. The integrated circuit of claim 3 , wherein the memory buffer is coupled to the unidirectional differential point-to-point channel.
5. The integrated circuit of claim 4 , wherein the host is coupled to the unidirectional differential point-to-point channel.
6. The integrated circuit of claim 4 , wherein the host is coupled to the unidirectional differential point-to-point channel.
7. An integrated circuit to provide a memory buffer to isolate one or more dynamic random access memory devices (DRAM devices) from a unidirectional differential point-to-point channel, the integrated circuit comprising:
an inbound redrive circuit to receive and redrive signals on an inbound path of the unidirectional differential point-to-point channel, the inbound redrive circuit including, at least in part, two or more bit-lanes for the inbound path of the unidirectional differential point-to-point channel;
an idle pattern generator coupled with the inbound redrive circuit, the idle pattern generator to provide a permuting data pattern if the memory buffer is not sending requested data to a host, wherein the permuting data pattern is generated by a 12-bit linear-feedback shift register (LFSR);
an outbound redrive circuit to receive and redrive signals on an outbound path of the unidirectional differential point-to-point channel, the outbound redrive circuit including, at least in part, two or more bit-lanes for the outbound path of the unidirectional differential point-to-point channel;
a double data rate (DDR) memory interface to couple the memory buffer with the one or more DRAM devices, the memory interface to receive data from the outbound redrive circuit and to send data to the inbound redrive circuit; and
a failover circuit coupled with the inbound redrive circuit, the failover circuit capable of redirecting a signal from a first bit-lane of the inbound path of the unidirectional point-to-point channel to a second bit-lane of the inbound path of the unidirectional point-to-point channel.
8. The integrated circuit of claim 7 , wherein the integrated circuit is attached to a printed circuit board (PCB).
9. The integrated circuit of claim 8 , wherein at least one DRAM device is attached to the PCB.
10. The integrated circuit of claim 9 , wherein the memory buffer is coupled to the unidirectional differential point-to-point channel.
11. The integrated circuit of claim 10 , wherein the host is coupled to the unidirectional differential point-to-point channel.