FINFET transistor having a doped subfin structure to reduce channel to substrate leakage
View Patent ↗An apparatus is described. The apparatus includes a FINFET device having a channel. The channel is composed of a first semiconductor material that is epitaxially grown on a subfin structure beneath the channel. The subfin structure is composed of a second semiconductor material that is different than the first semiconductor material. The subfin structure is epitaxially grown on a substrate composed of a third semiconductor material that is different than the first and second semiconductor materials. The subfin structure has a doped region to substantially impede leakage currents between the channel and the substrate.
1. An apparatus, comprising:
a FINFET device comprising a channel comprising a first semiconductor material that is epitaxially grown on a subfin structure beneath the channel, the subfin structure comprising a second semiconductor material that is different than the first semiconductor material, the subfin structure being epitaxially grown on a substrate comprising a third semiconductor material that is different than the first and second semiconductor materials, the subfin structure in a trench in a dielectric layer, the dielectric layer having a bottom surface, and the subfin structure having an upper region above a doped region, the doped region to substantially impede leakage currents between the channel and the substrate, wherein the doped region has a bottom surface below the bottom surface of the dielectric layer, wherein the doped region has a top surface above the bottom surface of the dielectric layer, and wherein the doped region has a higher concentration of dopants than a concentration of dopants in the upper region of the subfin structure.
2. The apparatus of claim 1 wherein the doped region is a p type doped region.
3. The apparatus of claim 2 wherein the p type doped region comprises any of:
carbon;
manganese;
zinc.
4. The apparatus of claim 1 wherein the substrate comprises silicon.
5. The apparatus of claim 4 wherein the subfin structure comprises any of:
gallium arsenide;
indium phosphide;
indium aluminum arsenide;
indium arsenide;
indium gallium arsenide;
indium antimony;
indium arsenide antimony.
6. The apparatus of claim 1 wherein the subfin structure comprises any of:
gallium arsenide;
indium phosphide;
indium aluminum arsenide;
indium arsenide;
indium gallium arsenide;
indium antimony;
indium arsenide antimony.
7. The apparatus of claim 1 wherein the doped region is closer to the substrate than to the channel.
8. A computing system, comprising:
one or more processing cores;
a system memory;
a memory controller coupled to the system memory;
a networking interface;
a semiconductor chip comprising a FINFET transistor, said FINFET transistor comprising a channel, said channel comprising a first semiconductor material that is epitaxially grown on a subfin structure beneath the channel, the subfin structure comprising a second semiconductor material that is different than the first semiconductor material, the subfin structure in a trench in a dielectric layer, the dielectric layer having a bottom surface, and the subfin structure being epitaxially grown on a substrate comprising a third semiconductor material that is different than the first and second semiconductor materials, the subfin structure having an upper region above a doped region, the doped region to substantially impede leakage currents between the channel and the substrate, wherein the doped region has a bottom surface below the bottom surface of the dielectric layer, wherein the doped region has a top surface above the bottom surface of the dielectric layer, and wherein the doped region has a higher concentration of dopants than a concentration of dopants in the upper region of the subfin structure.
9. The computing system of claim 8 wherein the doped region is a p type doped region.
10. The computing system of claim 9 wherein the p type doped region comprises any of:
carbon;
manganese;
zinc.
11. The computing system of claim 8 wherein the substrate comprises silicon.
12. The computing system of claim 11 wherein the subfin structure comprises any of:
gallium arsenide;
indium phosphide;
indium aluminum arsenide;
indium arsenide;
indium gallium arsenide;
indium antimony;
indium arsenide antimony.
13. The computing system of claim 8 wherein the subfin structure comprises any of:
gallium arsenide;
indium phosphide;
indium aluminum arsenide,
indium arsenide;
indium gallium arsenide;
indium antimony;
indium arsenide antimony.
14. The computing system of claim 8 wherein the channel is comprised of gallium arsenide doped to be n type.