Method and apparatus for improving stability of a 6T CMOS SRAM cell
View Patent ↗The present invention is a CMOS SRAM cell comprising two access devices, each access device comprised of a tri-gate transistor having a single fin; two pull-up devices, each pull-up device comprised of a tri-gate transistor having a single fin; and two pull-down devices, each pull-down device comprised of a tri-gate transistor having multiple fins. A method for manufacturing the CMOS SRAM cell, including the dual fin tri-gate transistor is also provided.
1. A method of forming a semiconductor device, comprising:
forming a silicon film on a substrate;
forming a sacrificial block on the silicon film, the sacrificial block having laterally opposite sidewalls;
depositing an insulating layer over the sacrificial block and the silicon film;
forming an insulating spacer on each of the laterally opposite sidewalls of the sacrificial block by performing an anisotropic etch on the insulating layer;
removing the sacrificial block;
forming two silicon fins by etching through the silicon film to the substrate using the insulating spacers as a mask, wherein each silicon fin has a top surface and a pair of laterally opposite sidewalls;
removing the insulating spacers to expose the top surface of each silicon fin; and
forming a gate dielectric layer on the top surface and on the sidewalls of each silicon fin by atomic layer deposition (ALD), wherein each silicon fin has at least one corner with a radius of curvature of less than 10 nm being defined by the atomic layer deposition of the gate dielectric layer at the corner of the silicon fin.
2. The method of claim 1 , wherein the substrate is an insulating substrate.
3. The method of claim 2 , wherein the sacrificial block is comprised of nitride.
4. The method of claim 1 , wherein the insulating layer is comprised of an oxide layer.
5. The method of claim 1 , wherein the thickness of the silicon film is 60 nm.
6. The method of claim 1 , wherein the laterally opposite sidewalls of the sacrificial block are 60 nm apart.
7. The method of claim 1 , wherein the sacrificial block is defined by lithography.
8. The method of claim 1 , wherein the thickness of the insulating layer is between 40 and 80 nm.
9. The method of claim 1 , wherein the thickness of the insulating layer is 60 nm.
10. The method of claim 1 , wherein the two silicon fins are separated by a distance of 60 nm or less.
11. The method of claim 1 , further comprising depositing a gate material over the top surface and sidewalls of each silicon fin and over the insulating substrate.
12. The method of claim 11 , further comprising patterning the gate material to form a gate electrode on the gate dielectric layer.
13. The method of claim 12 , further comprising forming a pair of source/drain regions in each silicon fin on opposite sides of the gate electrode.