Polarization gate stack SRAM
One embodiment provides an apparatus. The apparatus includes a first inverter comprising a first pull up transistor and a first pull down transistor; a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor; a first access transistor coupled to the first inverter; and a second access transistor coupled to the second inverter. A gate electrode of one transistor of each inverter comprises a polarization layer.
1. An SRAM memory cell, comprising:
a first invertor having a first pull up transistor and a first pull down transistor, wherein the first pull down transistor comprises a first gate stack having a ferroelectric material between a gate oxide and a channel of the first pull down transistor, the ferroelectric material in contact with the gate oxide;
a first access transistor coupled to the first invertor, wherein the first access transistor comprises a second gate stack having a ferroelectric material;
a second invertor having a second pull up transistor and a second pull down transistor; and
a second access transistor coupled to the second invertor.
2. The SRAM memory cell of claim 1 , wherein the second pull down transistor comprises a third gate stack having a ferroelectric material.
3. The SRAM memory cell of claim 1 , wherein the second access transistor comprises a third gate stack having a ferroelectric material.
4. The SRAM memory cell of claim 1 , wherein the second pull down transistor comprises a third gate stack having a ferroelectric material, and wherein the second access transistor comprises a fourth gate stack having a ferroelectric material.
5. The SRAM memory cell of claim 1 , wherein the ferroelectric material of the first gate stack is between and in contact with a first gate oxide and a channel of the first pull down transistor, and wherein the ferroelectric material of the second gate stack is between and in contact with a second gate oxide and a channel of the first access transistor.
6. The SRAM memory cell of claim 1 , wherein the ferroelectric material of the first gate stack and the ferroelectric material of the second gate stack comprise hafnium and oxygen.
7. An SRAM memory cell, comprising:
a first invertor having a first pull up transistor and a first pull down transistor, wherein the first pull down transistor comprises a first gate stack having a polarization layer between a gate oxide and a channel of the first pull down transistor, the polarization layer in contact with the gate oxide;
a first access transistor coupled to the first invertor, wherein the first access transistor comprises a second gate stack having a polarization layer;
a second invertor having a second pull up transistor and a second pull down transistor; and
a second access transistor coupled to the second invertor.
8. The SRAM memory cell of claim 7 , wherein the second pull down transistor comprises a third gate stack having a polarization layer.
9. The SRAM memory cell of claim 7 , wherein the second access transistor comprises a third gate stack having a polarization layer.
10. The SRAM memory cell of claim 7 , wherein the second pull down transistor comprises a third gate stack having a polarization layer, and wherein the second access transistor comprises a fourth gate stack having a polarization layer.
11. The SRAM memory cell of claim 7 , wherein the polarization layer of the first gate stack is between and in contact with a first gate oxide and a channel of the first pull down transistor, and wherein the polarization layer of the second gate stack is between and in contact with a second gate oxide and a channel of the first access transistor.
12. The SRAM memory cell of claim 7 , wherein the polarization layer of the first gate stack and the polarization layer of the second gate stack comprise hafnium and oxygen.
13. A system, comprising:
a processor; and
a memory array coupled to the processor, the memory array comprising an SRAM memory cell, and the SRAM memory cell comprising:
a first invertor having a first pull up transistor and a first pull down transistor, wherein the first pull down transistor comprises a first gate stack having a ferroelectric material between a gate oxide and a channel of the first pull down transistor, the ferroelectric material in contact with the gate oxide;
a first access transistor coupled to the first invertor, wherein the first access transistor comprises a second gate stack having a ferroelectric material;
a second invertor having a second pull up transistor and a second pull down transistor; and
a second access transistor coupled to the second invertor.
14. The system of claim 13 , further comprising:
a memory controller; and
a memory, wherein the memory controller is configured to couple the processor to the memory.
15. The system of claim 13 , further comprising:
a peripheral device coupled to the processor.
16. The system of claim 15 , wherein the peripheral device is a user interface selected from the group consisting of a keypad, a keyboard, a touch pad, a mouse, a display, and a touch sensitive display.
17. The system of claim 15 , wherein the peripheral device is a sensor selected from the group consisting of an accelerometer, a global positioning system, and a gyroscope.
18. The system of claim 15 , wherein the peripheral device is a storage device selected from the group consisting of a hard disk drive and a solid state drive.
19. The system of claim 13 , wherein the memory array and the processor are on a same die.
20. The system of claim 13 , wherein the system is selected from the group consisting of a mobile telephone, a smart phone, a wearable device, an Internet of Things networked device, a sensor system, and a computing system.