Polarization gate stack SRAM
One embodiment provides an apparatus. The apparatus includes a first inverter comprising a first pull up transistor and a first pull down transistor; a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor; a first access transistor coupled to the first inverter; and a second access transistor coupled to the second inverter. A gate electrode of one transistor of each inverter comprises a polarization layer.
1. An apparatus comprising:
a first inverter comprising a first pull up transistor and a first pull down transistor;
a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor;
a first access transistor coupled to the first inverter; and
a second access transistor coupled to the second inverter, a gate stack of one transistor of each inverter comprising a polarization layer between and in contact with a gate oxide and a respective channel of each transistor that comprises the polarization layer.
2. The apparatus of claim 1 , wherein each pull down transistor comprises the polarization layer.
3. The apparatus of claim 1 , wherein each pull up transistor comprises the polarization layer.
4. The apparatus of claim 1 , wherein the first access transistor and the second access transistor each comprises a polarization layer.
5. The apparatus of claim 1 , wherein the polarization layer comprises a ferroelectric material selected from the group comprising BaTiO 3 (Barium titanium oxide), PbTiO 3 (Lead titanium oxide), Pb(Zr0.2Ti0.8)O 3 (Lead zirconium titanium oxide), BiFe0.95Ru0.05O 3 (Bismuth iron ruthenium oxide), HfOx (Hafnium oxide) and/or HfZrOx (Hafnium Zirconium Oxide).
6. The apparatus of claim 1 , wherein a gate stack of another transistor comprises a polarization layer sandwiched between a gate oxide layer and a gate metal layer.
7. The apparatus of claim 1 , wherein the polarization layer comprises a nanocrystal material selected from the group comprising Si (Silicon), Ge (Germanium), Si/Ge, Al (Aluminum), W (Tungsten) and/or TiN (Titanium nitride).
8. A memory array comprising:
a plurality of SRAM (static random access memory) memory cells, each memory cell comprising:
a first inverter comprising a first pull up transistor and a first pull down transistor, a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor, a first access transistor coupled to the first inverter, a second access transistor coupled to the second inverter, a gate stack of one transistor of each inverter comprising a polarization layer between and in contact with a gate oxide and a respective channel of each transistor that comprises the polarization layer.
9. The memory array of claim 8 , wherein each pull down transistor comprises the polarization layer.
10. The memory array of claim 8 , wherein each pull up transistor comprises the polarization layer.
11. The memory array of claim 8 , wherein the first access transistor and the second access transistor each comprises a polarization layer.
12. The memory of claim 8 , wherein the polarization layer comprises a ferroelectric material selected from the group comprising BaTiO 3 (Barium titanium oxide), PbTiO.sub.3 (Lead titanium oxide), Pb(Zr0.2Ti0.8)O 3 (Lead zirconium titanium oxide), BiFe0.95Ru0.05O 3 (Bismuth iron ruthenium oxide), HfOx (Hafnium oxide) and/or HfZrOx (Hafnium Zirconium Oxide).
13. The memory of claim 8 , wherein a gate stack of another transistor comprises a polarization layer sandwiched between a gate oxide layer and a gate metal layer.
14. The memory of claim 8 , wherein the polarization layer comprises a nanocrystal material selected from the group comprising Si (Silicon), Ge (Germanium), Si/Ge, Al (Aluminum), W (Tungsten) and/or TiN (Titanium nitride).
15. A system comprising:
a processor comprising at least one core; and
a memory array comprising a plurality of static random access memory (SRAM) memory cells, each SRAM memory cell comprising:
a first inverter comprising a first pull up transistor and a first pull down transistor, a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor, a first access transistor coupled to the first inverter, a second access transistor coupled to the second inverter, a gate stack of one transistor of each inverter comprising a polarization layer between and in contact with a gate oxide and a respective channel of each transistor that comprises the polarization layer.
16. The system of claim 15 , wherein each pull down transistor comprises the polarization layer.
17. The system of claim 15 , wherein each pull up transistor comprises the polarization layer.
18. The system of claim 15 , wherein the first access transistor and the second access transistor each comprises a polarization layer.
19. The system of claim 15 , wherein the polarization layer comprises a ferroelectric material selected from the group comprising BaTiO 3 (Barium titanium oxide), PbTiO 3 (Lead titanium oxide), Pb(Zr0.2Ti0.8)O 3 (Lead zirconium titanium oxide), BiFe0.95Ru0.05O 3 (Bismuth iron ruthenium oxide), HfOx (Hafnium oxide) and/or HfZrOx (Hafnium Zirconium Oxide).
20. The system of claim 15 , wherein a gate stack of another transistor comprises a polarization layer sandwiched between a gate oxide layer and a gate metal layer of each gate stack.
21. The system of claim 15 , wherein the polarization layer comprises a nanocrystal material selected from the group comprising Si (Silicon), Ge (Germanium), Si/Ge, Al (Aluminum), W (Tungsten) and/or TiN (Titanium nitride).