Package substrate first-level-interconnect architecture
Embodiments of the present disclosure may relate to a package substrate that may include a layer having a layer surface that is planarized and a via within the layer, where the via includes a via surface that is exposed on the layer surface, and where the via surface is planarized. The package substrate may further include a bond pad on the layer surface, where a first thickness of the bond pad includes a seed layer on the via surface, and where a second thickness of the bond pad includes a plating stack on the seed layer. Other embodiments may be described or claimed.
1. A package substrate, comprising:
a layer having a layer surface that is planarized;
a via within the layer, wherein the via includes a via surface that is exposed on the layer surface, and wherein the via surface is planarized; and
a bond pad on the layer surface, wherein a first thickness of the bond pad includes a seed layer on the via surface, and wherein a second thickness of the bond pad includes a plating stack on the seed layer, wherein the plating stack is a nickel-palladium-gold stack, and wherein the nickel is in direct contact on the seed layer, the palladium is in direct contact on the nickel, and the gold is in direct contact on the palladium.
2. The package substrate of claim 1 , wherein the seed layer is a titanium-copper (Ti—Cu) layer, and wherein the titanium is on the layer surface, and wherein the copper is on the titanium.
3. The package substrate of claim 2 , wherein a thickness of the titanium is less than 0.5 micrometers (um) and a thickness of the copper is less than 2.5 um.
4. The package substrate of claim 1 , wherein the seed layer is one of a titanium layer or a tungsten-copper layer, wherein the tungsten is on the layer surface, and wherein the copper is on the tungsten, or a tantalum-copper layer, wherein the tantalum is on the layer surface, and wherein the copper is on the tantalum.
5. The package substrate of claim 1 , wherein a thickness of the nickel is less than 10 um, a thickness of the palladium is less than 0.5 um, and a thickness of the gold is less than 5 um.
6. The package substrate of claim 1 , wherein the plating stack is one of an electrolytic stack or an electroless plating stack.
7. The package substrate of claim 1 , further comprising solder on the bond pad.
8. An integrated circuit (IC) package, comprising:
a package substrate, wherein the package substrate includes,
a dielectric layer having a dielectric surface that is planarized;
a via buried in the dielectric layer, wherein the via includes a via surface that is exposed on the dielectric surface, and wherein the via surface is planarized; and
a bond pad on the dielectric surface, wherein a first thickness of the bond pad includes a surface finish on the via surface, and wherein a second thickness of the bond pad includes a plating stack on the surface finish, wherein the plating stack is a nickel-palladium-gold stack, and wherein the nickel is in direct contact on top of the surface finish, the palladium is in direct contact on top of the nickel, and the gold is in direct contact on top of the palladium;
a die that includes an IC pad; and
a solder ball coupled with the bond pad and the IC pad, to form a first level interconnect between the package substrate and the die.
9. The IC package of claim 8 , wherein the surface finish is a seed layer that includes titanium and copper.
10. The IC package of claim 9 , wherein a thickness of the titanium is less than 0.5 micrometers (um) and a thickness of the copper is less than 2.5 um.
11. The IC package of claim 8 , wherein a thickness of the nickel is less than 10 um, a thickness of the palladium is less than 0.5 um, and a thickness of the gold is less than 5 um.
12. The IC package of claim 8 , wherein the plating stack is an electrolytic stack.
13. A method of producing a package substrate, comprising:
creating a via on a pad;
burying the via in a dielectric applied over the via and the pad;
planarizing the dielectric to reveal a top of the via through a flat surface of the dielectric;
depositing a seed layer over the flat surface, wherein the seed layer is to cover the via; and
plating a nickel-palladium-gold (NPG) stack on the seed layer over the via, wherein the nickel is in direct contact on the seed layer, the palladium is in direct contact on the nickel, and the gold is in direct contact on the palladium, and wherein the seed layer and the NPG stack form a bond pad on the via.
14. The method of claim 13 , wherein planarizing the dielectric to reveal the top of the via through the flat surface of the dielectric includes using a chemical process, a mechanical process, or a chemical-mechanical process (CMP) to planarize the dielectric to reveal the top of the via through the flat surface of the dielectric.
15. The method of claim 13 , further comprising:
defining a size or shape of the bond pad;
placing a lamination on the seed layer, wherein the lamination includes an opening over the via, and wherein the NPG stack is plated in the opening;
removing the lamination; and
removing the seed layer exposed by removal of the lamination.
16. The method of claim 13 , further comprising placing solder on the bond pad.
17. A package substrate, comprising:
a layer having a layer surface that is planarized;
a via within the layer, wherein the via includes a via surface that is exposed on the layer surface, and wherein the via surface is planarized; and
a bond pad on the layer surface, wherein a first thickness of the bond pad includes a seed layer on the via surface, and wherein a second thickness of the bond pad includes a plating stack on the seed layer, wherein the plating stack is a cobalt/tungsten alloy-palladium-gold stack, and wherein the cobalt/tungsten alloy is in direct contact on the seed layer, the palladium is in direct contact on the cobalt/tungsten alloy, and the gold is in direct contact on the palladium.
18. The package substrate of claim 1 , wherein the seed layer is a titanium-copper (Ti—Cu) layer, and wherein the titanium is on the layer surface, and wherein the copper is on the titanium.
19. The package substrate of claim 2 , wherein a thickness of the titanium is less than 0.5 micrometers (um) and a thickness of the copper is less than 2.5 um.
20. The package substrate of claim 17 , wherein the seed layer is one of a titanium layer or a tungsten-copper layer, wherein the tungsten is on the layer surface, and wherein the copper is on the tungsten, or a tantalum-copper layer, wherein the tantalum is on the layer surface, and wherein the copper is on the tantalum.
21. The package substrate of claim 1 , wherein the plating stack is one of an electrolytic stack or an electroless plating stack.