Multilevel programming of phase change memory cells
View Patent ↗A method for programming a phase change memory cell is discussed. A phase change memory cell includes a memory element of a phase change material having a first state, in which the phase change material is crystalline and has a minimum resistance level, a second state in which the phase change material is amorphous and has a maximum resistance level, and a plurality of intermediate states, in which the phase change material includes both crystalline regions and amorphous regions and has intermediate resistance levels. According to the method, a plurality of programming pulses are provided to the phase change memory cell; programming energies respectively associated to the programming pulses are lower than a threshold energy which is required to bring the phase change material to the second state.
1. A phase change memory device, comprising:
a plurality of phase change memory cells; and
a program circuit to provide a plurality of cell programming pulses having programming energies that are insufficient to bring phase change memory cells to a fully amorphous state, and to initialize a phase change memory by providing an initialization pulse having such amplitude and duration to bring a chalcogenide material to a fully reset state and then to a fully set state.
2. The phase change memory device of claim 1 , wherein said program circuit to provide at least a start programming pulse to bring said phase change memory cells to a start intermediate state and an adjust programming pulse to bring said phase change material to a target intermediate state having a target resistance level.
3. The phase change memory device of claim 1 , wherein said program circuit to repeatedly provide groups of said adjust programming pulses having a predetermined duration and an amplitude and further comprising a verify circuit to read said phase change memory cells after each group of said adjust programming pulses.
4. A system comprising:
a processing unit;
a nonvolatile phase change memory device including a plurality of phase change memory cells; and
a program circuit to provide a plurality of cell programming pulses having programming energies that are insufficient to bring phase change memory cells to a fully amorphous state, and to initialize a phase change memory by providing an initialization pulse having such amplitude and duration to bring a chalcogenide material to a fully reset state and then to a fully set state.
5. The system according to claim 4 , wherein said interface includes a dipole antenna.
6. The system of claim 4 , wherein said program circuit to maintain crystallites in said cells in all programming states.
7. The system of claim 4 , wherein said program circuit to prevent said cells from becoming substantially crystalline.
8. The system of claim 4 , wherein said program circuit to provide at least a start programming pulse to bring said phase change memory cells to a start intermediate state and an adjust programming pulse to bring said phase change material to a target intermediate state having a target resistance level.
9. The system of claim 8 , wherein said program circuit to repeatedly provide groups of said adjust programming pulses having a predetermined duration and an amplitude and further comprising a verify circuit to read said phase change memory cells after each group of said adjust programming pulses.