Dynamic power control for reducing voltage level of graphics controller component of memory controller based on its degree of idleness

1. A method comprising:

detecting a trigger condition;

in response to detecting the trigger condition, reducing a voltage applied to a graphics controller component of a memory controller, said reducing causing the voltage to be reduced below a voltage level required to maintain context information in said graphics controller component.

2. The method of claim 1 , further comprising:

prior to said reducing and in response to detecting the trigger condition, storing in an external memory said context information.

3. The method of claim 2 , further comprising:

prior to said reducing and after said storing, disabling clock signals for said graphics controller component.

4. The method of claim 3 , further comprising:

after said reducing, detecting issuance of a command for said graphics controller component; and

in response to detecting issuance of the command, increasing the voltage applied to the graphics controller component, said increasing causing the voltage to be increased to a voltage level required to support full operation of the graphics controller component.

5. The method of claim 4 , further comprising:

after said increasing, enabling the clock signals for said graphics controller component.

6. The method of claim 5 , further comprising:

after said enabling, transferring said context information from said external memory to said graphics controller component.

7. The method of claim 4 , further comprising:

enabling the clock signals for said graphics controller component after detecting issuance of said command and prior to said increasing.

8. The method of claim 1 , wherein said trigger condition is a degree of idleness of said graphics controller component.

9. The method of claim 8 , wherein said degree of idleness is a proportion of time in an idle condition relative to a previous time period.

10. The method of claim 8 , wherein said degree of idleness is a duration of a period of idleness.

11. The method of claim 1 , wherein said trigger condition is a process to reduce a voltage applied to a processor that is coupled to the memory controller.

12. An apparatus comprising a memory controller, the memory controller including a graphics controller component, and the memory controller also including a power management controller for controlling a supply of power for at least a portion of the memory controller, the power management controller operative to:

detect a trigger condition;

in response to detecting the trigger condition, reduce a voltage applied to the graphics controller component of the memory controller, said reduction causing the voltage to be reduced below a voltage level required to maintain context information in said graphics controller component.

13. The apparatus of claim 12 , wherein said power management controller is further operative to:

prior to said reduction and in response to detecting the trigger condition, store in an external memory said context information.

14. The apparatus of claim 13 , wherein said power management controller is further operative to:

prior to said reduction and after said storing, disable clock signals for said graphics controller component.

15. The apparatus of claim 14 , wherein said power management controller is further operative to:

after said reduction, detect issuance of a command for said graphics controller component; and

in response to detecting issuance of the command, increase the voltage applied to the graphics controller component, said increase causing the voltage to be increased to a voltage level required to support full operation of the graphics controller component.

16. The apparatus of claim 15 , wherein said power management controller is further operative to:

after said increase, enable the clock signals for said graphics controller component.

17. The apparatus of claim 16 , wherein said power management controller is further operative to:

after said enabling, transfer said context information from said external memory to said graphics controller component.

18. The apparatus of claim 15 , wherein said power management controller is further operative to:

enable the clock signals for said graphics controller component after detecting issuance of said command and prior to said increasing.

19. The apparatus of claim 12 , wherein said trigger condition is a degree of idleness of said graphics controller component.

20. The apparatus of claim 19 , wherein said degree of idleness is a proportion of time in an idle condition relative to a previous time period.

21. The apparatus of claim 19 , wherein said degree of idleness is a duration of a period of idleness.

22. The apparatus of claim 12 , wherein said trigger condition is a process to reduce a voltage applied to a processor that is coupled to the memory controller.

23. A system comprising:

a memory controller; and

a graphics memory unit in communication with the memory controller;

wherein the memory controller includes a graphics controller component, and the memory controller also includes a power management controller for controlling a supply of power for at least a portion of the memory controller, the power management controller operative to:

detect a trigger condition;

in response to detecting the trigger condition, reduce a voltage applied to the graphics controller component of the memory controller, said reduction causing the voltage to be reduced below a voltage level required to maintain context information in said graphics controller component.

24. The system of claim 23 , wherein said power management controller of the memory controller is further operative to:

prior to said reduction and in response to detecting the trigger condition, store in said graphics memory unit said context information.

25. The system of claim 24 , wherein said power management controller of the memory controller is further operative to:

prior to said reduction and after said storing, disable clock signals for said graphics controller component.