IP Library Granted Patent US 8,508,037
Granted Patent B2
US 8,508,037 · App. 12/962,358 · Granted Aug 13, 2013

Bumpless build-up layer and laminated core hybrid structures and methods of assembling same

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Quick Facts
Patent No.
US 8,508,037
App. No.
12/962,358
Granted
Aug 13, 2013
Kind
B2
Abstract

A structure includes a hybrid substrate for supporting a semiconductive device that includes a bumpless build-up layer in which the semiconductive device is embedded and a laminated-core structure. The bumpless build-up layer and the laminated-core structure are rendered an integral apparatus by a reinforcement plating that connects to a plated through hole in the laminated-core structure and to a subsequent bond pad of the bumpless build-up layer structure.

Claims (29)

1. A semiconductor apparatus comprising:

a semiconductive die embedded in a bumpless build-up layer (BBUL) structure; and

a laminated-core structure abutting the BBUL structure, wherein the laminated-core structure and the BBUL structure are electrically coupled by an electrically conductive body that is integral to both, wherein the electrically conductive body is a hollow cylinder that is closed on one end thereof.

2. The apparatus of claim 1 , wherein the laminated-core structure includes a copper plated through hole, wherein the BBUL structure includes a copper subsequent bond pad, and wherein the electrically conductive body is copper that is fused to the copper plated through hole and to the copper subsequent bond pad.

3. The apparatus of claim 1 , wherein the laminated-core structure includes a copper plated through hole (PTH) having a width in a range from 100 μm to 120 μm and a thickness in a range from 400 μm to 1,400 μm, wherein the BBUL structure includes a copper subsequent bond pad, and wherein the electrically conductive body is copper that is fused to the copper plated through hole and to the copper subsequent bond pad.

4. The apparatus of claim 1 , wherein the electrically conductive body is fused to a plated through hole in the laminated-core structure and to a subsequent bond pad on the BBUL structure.

5. The apparatus of claim 1 , wherein the semiconductor die is a first die, the apparatus further including a subsequent die embedded in the BBUL structure.

6. The apparatus of claim 1 , wherein the BBUL structure includes a die side, the apparatus further including a die-side contact pad.

7. The apparatus of claim 1 , wherein the BBUL structure includes a die side, the apparatus further including:

a die-side contact pad; and

a package-on-package apparatus mounted on the BBUL structure at the die side and electrically coupled at the die-side contact pad.

8. The apparatus of claim 1 , further including a foundation substrate, wherein the laminated core structure is mounted to the foundation substrate.

9. A semiconductive device comprising:

a die embedded in a bumpless build-up layer (BBUL), wherein the die includes an active surface and a backside surface, the BBUL including:

a dielectric first film and a first contact disposed in the dielectric first film and making contact with the die at the active surface; and

a dielectric subsequent film and a subsequent contact disposed in the dielectric subsequent film, wherein the subsequent contact is coupled to the first contact and further including a subsequent contact pad;

a laminated-core structure assembled at the subsequent contact pad, the laminated core further including:

a plated through hole (PTH) upon a PTH wall;

a reinforcement plating that is fused to the PTH and the subsequent contact pad, wherein the reinforcement plating is a hollow cylinder that is closed on one end thereof; and

a land-side structure including:

land-side contact pads that are coupled to the PTH at laminated-core land-interface bond pads.

10. The device of claim 9 , further including a foundation substrate assembled at the land-side contact pads.

11. The device of claim 9 , wherein the laminated-core structure includes a copper plated through hole, wherein the BBUL structure includes a copper subsequent bond pad, and wherein the reinforcement plating is copper that is fused to the copper plated through hole and to the copper subsequent bond pad.

12. The device of claim 9 , wherein the laminated-core structure includes a copper plated through hole (PTH) having a width in a range from 100 μm to 350 μm and a thickness in a range from 400 μm to 1,400 μm, wherein the BBUL structure includes a copper subsequent bond pad, and wherein the reinforcement plating is copper that is fused to the copper plated through hole and to the copper subsequent bond pad.

13. The device of claim 9 , wherein the semiconductor die is a first die, the device further including a subsequent die embedded in the BBUL structure.

14. The device of claim 9 , wherein the BBUL structure includes a die side, the device further including a die-side contact pad.

15. The device of claim 9 , wherein the BBUL structure includes a die side, the device further including:

a die-side contact pad; and

a package-on-package apparatus mounted on the BBUL structure at the die side and electrically coupled at the die-side contact pad.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2010
From: MANUSHAROW, MATHEW J.; HLAD, MARK S.; NALLA, RAVI K.
To: INTEL CORPORATION
Reel/Frame 025481/0334 →