Processing packet sequence using same function set pipelined multiple threads spanning over multiple processing engines and having exclusive data access

1. A method, comprising:

processing a sequence of packets with a sequence of threads, the sequence of threads spanning multiple programmable processing elements integrated within a processor, each of the programmable processing elements providing multiple threads of execution,

wherein the sequence of threads comprises a sub-sequence for each of the multiple programmable processing elements that include multiple threads provided by the respective programmable processing elements,

wherein each packet is processed by a single one of the threads in the sequence of threads and each thread processes a single packet in the sequence of packets,

wherein each of the threads performs the same set of functions, and

wherein each of the threads acquires exclusive modification access to data shared by multiple ones of the threads.

2. The method of claim 1 ,

wherein the threads comprise threads divided into M pipeline stages, where M is a positive integer greater than one; and

wherein the multiple programmable processing elements comprise M programmable processing elements.

3. The method of claim 1 , wherein the threads comprise threads divided into multiple pipeline stages of the same duration.

4. The method of claim 3 , wherein each individual pipeline stage is completed by all the threads in a one of the programmable processing elements before being completed by all the threads in a successive one of the programmable processing elements in the sequence of threads.

5. The method of claim 1 , wherein the data shared by multiple threads comprises data shared by threads provided by the same programmable processing elements.

6. The method of claim 1 , wherein the data shared by multiple threads comprises data shared by threads provided by different programmable processing elements.

7. An article of manufacture comprising instructions for causing a processor to:

processor a sequence of packets with a sequence of threads, the sequence of threads spanning multiple programmable processing elements integrated within a processor, each of the programmable processing elements providing multiple threads of execution,

wherein the sequence of threads comprises a sub-sequence for each of the multiple programmable processing elements that include multiple threads provided by the respective programmable processing elements,

wherein each packet is processed by a single one of the threads in the sequence of threads and each thread processes a single packet in the sequence of packets,

wherein each of the threads executes instructions to perform the same set of functions, and

wherein each of the threads executes instructions to acquire exclusive modification access to data shared by multiple threads.

8. The article of claim 7 ,

wherein the threads comprise threads divided into M pipeline stages, where M is a positive integer greater than one; and

wherein the multiple programmable processing elements comprising M programmable processing elements.

9. The article of claim 7 , wherein the threads comprise threads divided into multiple pipeline stages of the same duration.

10. The article of claim 9 , wherein each individual pipeline stage is completed by all the threads in a one of the programmable processing elements before being complete by all the threads in a successive one of the programmable processing elements in the sequence of threads.

11. The article of claim 7 , wherein the data shared by multiple threads comprises data shared by threads provided by the same programmable processing element.

12. The article of claim 7 , wherein the data shared by multiple threads comprises data shared by threads provided by different programmable processing elements.

13. A system comprising:

a processor comprising:

multiple programmable processing elements, each of the processing elements having multiple program counters for multiple threads of execution; and

an article of manufacture comprising instructions for causing a processor to:

process a sequence of packets with a sequence of threads, the sequence of threads spanning multiple programmable processing elements integrated within a processor, each of the programmable processing elements providing multiple threads of execution,

wherein the sequence of threads comprises a sub-sequence for each of the multiple programmable processing elements that includes multiple threads provided by the respective programmable processing elements,

wherein each packet is processed by a single one of the threads in the sequence of threads and each thread processes a single packet in the sequence of packets,

wherein each of the threads executes instructions to perform the same set of functions, and

wherein each of the threads executes instructions to acquire exclusive modification access to data shared by multiple threads.

14. The system of claim 13 ,

wherein the threads comprise threads divided into M pipeline stages, where M is a positive integer greater than one; and

wherein the multiple programmable processing elements comprise M programmable processing elements.

15. The system of claim 13 , wherein the threads comprise threads divided into multiple pipeline stages of the same duration.

16. The system of claim 15 , wherein each individual pipeline stage is completed by all the threads in a one of the programmable processing elements before being completed by all the threads in a successive one of the programmable processing elements in the sequence of threads.

17. The system of claim 13 , wherein the data shared by multiple threads comprises data shared by threads provided by the same programmable processing element.

18. The system of claim 13 , wherein the data shared by multiple threads comprises data shared by threads provided by different programmable processing elements.