Multiply add functional unit capable of executing scale, round, getexp, round, getmant, reduce, range and class instructions

1. A processor comprising:

a decode unit to decode a first floating point instruction, the first floating point instruction to indicate at least a floating point value X; and

an execution unit to execute a plurality of floating point instructions including the first floating point instruction and a floating point multiply add instruction, the execution unit including:

at least an exponent calculation logic, a mantissa calculation logic that includes a multiplier, and a rounder to generate a floating point result R that is to include a reduced argument of the floating point value X based on a parameter M that is to be provided as an input for the first floating point instruction and that is to represent a number of binary places,

wherein R=X −(Round(2 M *X ))*2 −M , and

wherein said Round represents a round operation; and

a write logic circuitry to store the floating point result R.

2. The processor of claim 1 , wherein the round operation is to round a mantissa of the floating point value X to the number of binary places.

3. The processor of claim 1 , wherein the first floating point instruction has a parameter to specify the round operation to be any one of a round up round operation, a round down round operation, and a round to a nearest even number round operation.

4. The processor of claim 1 , wherein the execution unit comprises a masking layer.

5. The processor of claim 4 , wherein the floating point result R is part of a packed operand, and wherein the masking layer is to present arithmetic exceptions that occur for valid floating point results of the packed operand and is to suppress presenting arithmetic exceptions that occur for floating point results of the packed operand that are not valid.

6. The processor of claim 1 , wherein the floating point value X is a scalar single precision floating point value.

7. The processor of claim 1 , wherein the floating point value X is a scalar double precision floating point value.

8. The processor of claim 1 , wherein the floating point value X is one of a plurality of single precision floating point values in a packed operand.

9. The processor of claim 1 , wherein the floating point value X is one of a plurality of double precision floating point values in a packed operand.

10. The processor of claim 1 , wherein the decode unit and the execution unit are disposed on a semiconductor chip.

11. The processor of claim 1 , wherein the processor is a Complex Instruction Set (CISC) architecture processor.

12. A processor comprising:

a decode unit to decode a first floating point instruction, the first floating point instruction to indicate a first floating point term X and a second floating point term Y; and

an execution unit to execute a plurality of floating point instructions including the first floating point instruction and a floating point multiply add instruction, the execution unit including:

at least an exponent calculation logic and a mantissa calculation logic, which includes a multiplier, to scale the first floating point term X by a floor of the second floating point term Y to generate a floating point result R,

wherein R =( X )*2 (floor:Y) , and

wherein the floor:Y represents the floor of the second floating point term Y which is an integer expression of the second floating point term Y that drops fractional bits of the second floating point term Y; and

write logic circuitry to store the floating point result R.

13. The processor of claim 12 , wherein a mantissa of the floating point result R is equal to a mantissa of the first floating point term X, and an exponent of the floating point result R is equal to an exponent of the first floating point term X plus the floor of the second floating point term Y.

14. The processor of claim 12 , wherein the floating point result R has a binary point of the first floating point term X moved by the floor of the second floating point term Y.

15. The processor of claim 12 , wherein the execution unit comprises a masking layer.

16. The processor of claim 15 , wherein the floating point result R is part of a packed operand, and wherein the masking layer is to present arithmetic exceptions that occur for valid floating point results of the packed operand and is to suppress presenting arithmetic exceptions that occur for floating point results of the packed operand that are not valid.

17. The processor of claim 12 , wherein the first floating point term X is a scalar single precision floating point term.

18. The processor of claim 12 , wherein the first floating point term Xis a scalar double precision floating point term.

19. The processor of claim 12 , wherein the first floating point term X is one of a plurality of single precision floating point terms in a packed operand.

20. The processor of claim 12 , wherein the first floating point term X is one of a plurality of double precision floating point terms in a packed operand.

21. The processor of claim 12 , wherein the decode unit and the execution unit are disposed on a semiconductor chip.

22. The processor of claim 12 , wherein the processor is a Complex Instruction Set (CISC) architecture processor.

23. A processor comprising:

a decode unit to decode a first floating point instruction, the first floating point instruction to indicate at least a floating point value and to specify a number of binary places; and

an execution unit to execute a plurality of floating point instructions including the first floating point instruction and a floating point multiply add instruction, the execution unit including:

at least a rounder and a mantissa calculation logic, which includes a multiplier, to round a mantissa of the floating point value to the specified number of binary places; and

write logic circuitry to store a floating point result that is to have the rounded mantissa and an exponent of the floating point value.

24. The processor of claim 23 , wherein the decode unit is to decode the first floating point instruction that is to specify a round mode to be used to round the mantissa of the floating point value.

25. The processor of claim 23 , wherein the execution unit is to round the mantissa of the floating point value based on any one of a round up round mode, a round down round mode, a round to nearest even number round mode, and a round to zero round mode.

26. The processor of claim 23 , wherein the execution unit is to drop a lowest ordered fractional bit string from the mantissa of the floating point value.

27. The processor of claim 23 , wherein the execution unit comprises a masking layer.

28. The processor of claim 27 , wherein the floating point result is part of a packed operand, and wherein the masking layer is to present arithmetic exceptions that occur for valid floating point results of the packed operand and is to suppress presenting arithmetic exceptions that occur for floating point results of the packed operand that are not valid.

29. The processor of claim 23 , wherein the floating point value is a scalar single precision floating point value.

30. The processor of claim 23 , wherein the floating point value is a scalar double precision floating point value.

31. The processor of claim 23 , wherein the floating point value is one of a plurality of single precision floating point values in a packed operand.

32. The processor of claim 23 , wherein the floating point value is one of a plurality of double precision floating point values in a packed operand.

33. The processor of claim 23 , wherein the decode unit and the execution unit are disposed on a semiconductor chip.

34. The processor of claim 23 , wherein the processor is a Complex Instruction Set (CISC) architecture processor.