Multiply add functional unit capable of executing scale, round, GETEXP, round, GETMANT, reduce, range and class instructions

1. A processor, comprising:

an instruction execution pipeline implemented with circuitry disposed on a semiconductor chip, said instruction execution pipeline comprising:

an instruction fetch unit to fetch instructions;

an instruction decode unit to decode the instructions; and

functional units to execute the instructions, a functional unit of the functional units to perform at least three different floating point instructions and having exponent difference calculation logic, a multiplier and an adder to support a first of the at least three different floating point instructions which is a multiply-add instruction, said functional unit also having a rounder to support a second of the at least three different floating point instructions which is a vector round instruction that specifies how many binary places each mantissa value of a vector of floating point values is to be rounded to, said exponent difference calculation logic having a shifter to support execution of said multiply-add instruction and said vector round instruction, wherein said vector round instruction is a different instruction than said multiply-add instruction, and wherein the functional unit is also able to perform at least one other instruction which is different than the multiply-add instruction and different than the vector round instruction.

2. The processor of claim 1 wherein said shifter is also to support a scale instruction to be executed by said functional unit.

3. The processor of claim 2 wherein said exponent difference calculation logic includes a second shifter to support execution of said multiply-add instruction, wherein, said second shifter is also to support a get exponent instruction to be executed by said functional unit.

4. The processor of claim 1 wherein said exponent difference calculation logic includes a second shifter to support execution of said multiply-add instruction,

wherein, said second shifter is also to support a get exponent instruction to be executed by said functional unit.

5. The processor of claim 4 wherein said shifter, said second shifter and said rounder are also support a reduce instruction to be executed by said functional unit.

6. The processor of claim 1 wherein said shifter and said rounder are also to support a reduce instruction to be executed by said functional unit.

7. A method, comprising:

fetching a first of at least three different floating-point instructions with an instruction fetch unit of an instruction execution pipeline implemented with circuitry on a semiconductor chip;

decoding said first instruction with an instruction decode unit of said instruction execution pipeline;

executing said first instruction with a functional unit of said instruction execution pipeline, said first instruction being a multiply-add instruction;

fetching a second of the at least three different floating point instructions with said instruction fetch unit of said instruction execution pipeline;

decoding said second instruction with said instruction decode unit;

executing said second instruction with said functional unit, said second instruction being a vector round instruction wherein said vector round instruction is a different instruction than said multiply-add instruction, and wherein the functional unit is also able to perform at least one other instruction which is different than the multiply-add instruction and different than the vector round instruction.

8. The method of claim 7 further comprising executing a third instruction with said functional unit, said third instruction being a scale instruction.

9. The method of claim 8 further comprising executing a fourth instruction with said functional unit, said fourth instruction being a get exponent instruction.

10. The method of claim 9 further comprising executing a filth instruction with said functional unit, said fifth instruction being a reduce instruction.

11. The method of claim 10 further comprising executing a sixth instruction with said functional unit, said sixth instruction being a get mantissa instruction.

12. The method of claim 11 further comprising executing a seventh instruction with said functional unit, said seventh instruction being a range instruction.

13. A computing system, comprising:

non-volatile storage unit; and

a processor, said processor having an instruction fetch unit, an instruction decode unit and a functional unit, said functional unit to perform at least three different floating point instructions and having exponent difference calculation logic, a multiplier and an adder to support a first of the at least three different floating point instructions which is a multiply-add instruction, said functional unit also having a rounder to support a second of the at least three different floating point instructions which is a round instruction that specifies how many binary places a mantissa value is to be rounded to, said exponent difference calculation logic having a shifter to support execution of said multiply-add and said round instruction, wherein the shifter is also to support a third of the at least three different floating point instructions which is a scale instruction to be executed by said functional unit, the scale instruction to scale a first floating point value by a floor of a second floating point value, and wherein said vector round instruction, said multiply-add instruction, and said scale instruction are all different instructions from each other.

14. The computer system of claim 13 , wherein said exponent difference calculation logic includes a second shifter to support execution of said multiply-add instruction, wherein, said second shifter is also to support a get exponent instruction to be executed by said functional unit.

15. The computer system of claim 13 wherein said exponent difference calculation logic includes a second shifter to support execution of said multiply-add instruction, wherein, said second shifter is also to support a gel exponent instruction to be executed by said functional unit.

16. The computer system of claim 15 wherein said shifter, said second shifter and said rounder are also to support a reduce instruction to be executed by said functional unit.

17. The computer system of claim 13 , wherein the round instruction comprises a vector round instruction.