IP Library Granted Patent US 10,338,474
Granted Patent B2
US 10,338,474 · App. 15/528,329 · Granted Jul 2, 2019

Underlying absorbing or conducting layer for Ebeam direct write (EBDW) lithography

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Quick Facts
Patent No.
US 10,338,474
App. No.
15/528,329
Granted
Jul 2, 2019
Kind
B2
Abstract

Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. Particular embodiments are directed to implementation of an underlying absorbing and/or conducting layer for ebeam direct write (EBDW) lithography.

Claims (35)

1. A method of patterning a resist layer using an e-beam tool, the method comprising:

providing a wafer having a resist layer directly on an underlying conducting layer; and

performing ebeam direct write lithography to pattern the resist layer with incident electrons, wherein the conducting layer reflects or conducts away a substantial portion of the incident electrons to diminish backscatter.

2. The method of claim 1 , wherein the underlying conducting layer is a material layer selected from the group consisting of a layer of chromium (Cr), a layer of molybdenum silicide (MoSi), a layer of titanium nitride (TiN), a layer of tantalum nitride (TaN), a layer of silicon (Si), a layer of graphene, a layer of tungsten (W), a layer of copper (Cu), and a layer of cobalt (Co).

3. The method of claim 1 , wherein the underlying conducting layer is a material layer selected from the group consisting of a layer of ruthenium (Ru), a layer of titanium (Ti), a layer of nickel (Ni), a layer of aluminum (Al), a layer of hafnium (Hf), a layer of tantalum (Ta), a layer of zirconium (Zr), or a layer of an alloy thereof.

4. The method of claim 1 , wherein the underlying conducting layer is a single material layer.

5. The method of claim 1 , wherein the underlying conducting layer is a stack of multiple material layers.

6. The method of claim 1 , wherein the underlying conducting layer has a thickness approximately in the range of 1-200 nanometers.

7. The method of claim 1 , wherein the wafer is provided further having an upper charge dissipation layer disposed above the resist layer.

8. The method of claim 1 , further comprising:

subsequent to performing the ebeam direct write lithography, developing the resist layer and etching the conducting layer and a layer below the conducting layer.

9. The method of claim 1 , wherein performing the ebeam direct write lithography comprises using an ebeam approximately in the range of 10 kEV to 200 kEV with a current approximately in the range of a few uC/cm 2 to hundreds of uC/cm 2 .

10. A method of patterning a resist layer using an e-beam tool, the method comprising:

providing a wafer having a resist layer directly on an underlying conducting layer; and

performing ebeam direct write lithography to pattern the resist layer with incident electrons, wherein the conducting layer reflects or conducts a substantial portion of the incident electrons to tune backscatter.

11. The method of claim 10 , wherein the underlying conducting layer is a material layer selected from the group consisting of a layer of chromium (Cr), a layer of molybdenum silicide (MoSi), a layer of titanium nitride (TiN), a layer of tantalum nitride (TaN), a layer of silicon (Si), a layer of graphene, a layer of tungsten (W), a layer of copper (Cu), and a layer of cobalt (Co).

12. The method of claim 10 , wherein the underlying conducting layer is a material layer selected from the group consisting of a layer of ruthenium (Ru), a layer of titanium (Ti), a layer of nickel (Ni), a layer of aluminum (Al), a layer of hafnium (Hf), a layer of tantalum (Ta), a layer of zirconium (Zr), or a layer of an alloy thereof.

13. The method of claim 10 , wherein the underlying conducting layer is a single material layer.

14. The method of claim 10 , wherein the underlying conducting layer is a stack of multiple material layers.

15. The method of claim 10 , wherein the underlying conducting layer has a thickness approximately in the range of 1-200 nanometers.

16. The method of claim 10 , wherein the wafer is provided further having an upper charge dissipation layer disposed above the resist layer.

17. The method of claim 10 , further comprising:

subsequent to performing the ebeam direct write lithography, developing the resist layer and etching the conducting layer and a layer below the conducting layer.

18. The method of claim 10 , wherein performing the ebeam direct write lithography comprises using an ebeam approximately in the range of 10 kEV to 200 kEV with a current approximately in the range of a few uC/cm 2 to hundreds of uC/cm 2 .

19. A material stack for patterning using an e-beam tool, the material stack comprising:

a wafer having a layer for patterning;

an underlying conducting layer disposed above the layer for patterning; and

a resist layer disposed directly on the underlying conducting layer.

20. The material stack of claim 19 , wherein the underlying conducting layer is a material layer selected from the group consisting of a layer of chromium (Cr), a layer of molybdenum silicide (MoSi), a layer of titanium nitride (TiN), a layer of tantalum nitride (TaN), a layer of silicon (Si), a layer of graphene, a layer of tungsten (W), a layer of copper (Cu), and a layer of cobalt (Co).

21. The material stack of claim 19 , wherein the underlying conducting layer is a material layer selected from the group consisting of a layer of ruthenium (Ru), a layer of titanium (Ti), a layer of nickel (Ni), a layer of aluminum (Al), a layer of hafnium (Hf), a layer of tantalum (Ta), a layer of zirconium (Zr), or a layer of an alloy thereof.

22. The material stack of claim 19 , wherein the underlying conducting layer is a single material layer.

23. The material stack of claim 19 , wherein the underlying conducting layer is a stack of multiple material layers.

24. The material stack of claim 19 , wherein the underlying conducting layer has a thickness approximately in the range of 1-200 nanometers.

25. The material stack of claim 19 , further comprising:

an upper charge dissipation layer disposed above the resist layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →