Techniques to couple high bandwidth memory device on silicon substrate and package substrate
Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.
1. An apparatus comprising:
a mode register to indicate a mode of operation for a high bandwidth memory stack device to include a plurality of memory devices stacked above a logic layer; and
circuitry at the logic layer to execute logic, the logic to:
read a bit value of the mode register; and
cause, based on the bit value of the mode register, a portion of input/output (I/O) contacts on a bottom side of the logic layer to be active and a remaining portion of the I/O contacts to be inactive, the portion of I/O contacts arranged to receive or transmit I/O signals for one or more data channels to access the plurality of memory devices.
2. The apparatus of claim 1 , further comprising the logic to:
cause I/O signals to be routed via the one or more data channels through the portion of I/O contacts such that a redirection layer below the logic layer enables the high bandwidth memory stack device to connect with a package substrate through a reduced number of I/O contacts.
3. The apparatus of claim 1 , comprising the logic to cause the I/O signals to be routed via the one or more data channels through the portion of I/O contacts at a first transfer rate per second that is twice a second transfer rate per second if the I/O signals were routed via the one or more data channels through both the portion of I/O contacts and the remaining portion of I/O contacts.
4. The apparatus of claim 2 , comprising the high bandwidth memory stack device to connect with the package substrate via first contacts having a larger pitch between the first contacts compared to second contacts that correspond to both active and inactive I/O contacts on the bottom side of the logic layer.
5. The apparatus of claim 4 , comprising the package substrate including I/O signal paths routed between the high bandwidth memory device and a central processing unit or a graphics processing unit, the I/O signal paths to couple with the first contacts.
6. The apparatus of claim 1 , comprising the portion and the remaining portion of I/O contacts included in a plurality of I/O contacts for a first data channel from among the one or more data channels, the first data channel to access a memory array at a memory device from among the plurality of memory devices, the portion to include half of the plurality of I/O contacts.
7. The apparatus of claim 1 , comprising the portion of I/O contacts and the remaining portion of I/O contacts included in a plurality of I/O contacts for a first data channel and a second data channel from among the one or more data channels, the first data channel to access a first memory array at a memory device from among the plurality of memory devices, the second data channel to access a second memory array at the memory device, the portion to include half of the plurality of I/O contacts for the first and the second data channels.
8. The apparatus of claim 7 , further comprising the logic to:
cause, based on the bit value of the mode register, a portion of command and address (CA) contacts on the bottom side of the logic layer to be active and a remaining portion of the CA contacts to be inactive, the portion of CA contacts arranged to receive or transmit CA signals for the first and the second data channels to facilitate access to the plurality of memory devices; and
cause CA signals for the first and the second data channels to be routed through the portion of CA contacts such that a redirection layer below the logic layer enables the high bandwidth memory stack device to connect with a package substrate through a reduced number of CA contacts.
9. The apparatus of claim 1 , comprising the plurality of memory devices including dynamic random access memory.
10. A method comprising:
determining, via a mode register, a mode of operation for a high bandwidth memory stack device include a plurality of memory devices stacked above a logic layer; and
causing, based on the determined mode of operation, a portion of input/output (I/O) contacts on a bottom side of the logic layer to be active and a remaining portion of the I/O contacts to be inactive, the portion of I/O contacts arranged to receive or transmit I/O signals for one or more data channels to access the plurality of memory devices.
11. The method of claim 10 , further comprising:
causing I/O signals to be routed via the one or more data channels through the portion of I/O contacts such that a redirection layer below the logic layer enables the high bandwidth memory stack device to connect with a package substrate through a reduced number of I/O contacts.
12. The method of claim 10 , further comprising:
causing the I/O signals to be routed via the one or more data channels through the portion of I/O contacts at a first transfer rate per second that is twice a second transfer rate per second if the I/O signals were routed via the one or more data channels through both the portion of I/O contacts and the remaining portion of I/O contacts.
13. The method of claim 11 , comprising the high bandwidth memory stack device to connect with the package substrate via first contacts having a larger pitch between the first contacts compared to second contacts that correspond to both active and inactive I/O contacts on the bottom side of the logic layer.
14. The method of claim 10 , comprising the portion and the remaining portion of I/O contacts included in a plurality of I/O contacts for a first data channel from among the one or more data channels, the first data channel to access a memory array at a memory device from among the plurality of memory devices, the portion to include half of the plurality of I/O contacts.
15. The method of claim 10 , comprising the portion of I/O contacts and the remaining portion of I/O contacts included in a plurality of I/O contacts for a first data channel and a second data channel from among the one or more data channels, the first data channel to access a first memory array at a memory device from among the plurality of memory devices, the second data channel to access a second memory array at the memory device, the portion to include half of the plurality of I/O contacts for the first and the second data channels.
16. The method of claim 15 , further comprising:
causing, based on the determined mode of operation, a portion of command and address (CA) contacts on the bottom side of the logic layer to be active and a remaining portion of the CA contacts to be inactive, the portion of CA contacts arranged to receive or transmit CA signals for the first and the second data channels to facilitate access to the plurality of memory devices; and
causing CA signals for the first and the second data channels to be routed through the portion of CA contacts such that a redirection layer below the logic layer enables the high bandwidth memory stack device to connect with a package substrate through a reduced number of CA contacts.