Stacked-die packages with silicon vias and surface activated bonding
View Patent ↗In some embodiments, an apparatus and a system are provided. The apparatus and the system may comprise a first integrated circuit die comprising a plurality of silicon vias and a first surface activated bonding site coupled to the plurality of silicon vias, and a second integrated circuit die comprising a second surface activated bonding site coupled to the first surface activated bonding site. The first surface activated bonding site may comprise a first clean metal and the second surface activated bonding site may comprise a second clean metal. If the first surface activated bonding site is coupled to the second surface activated bonding site respective metal atoms of the first activated surface activated bonding site are diffused into the second surface activated bonding site and respective metal atoms of the second activated surface activated bonding site are diffused into the first surface activated bonding site.
1. An apparatus comprising:
a first integrated circuit die comprising a plurality of silicon vias and a first surface activated bonding site coupled to the plurality of silicon vias; and
a second integrated circuit die comprising a second surface activated bonding site coupled to the first surface activated bonding site, wherein the first surface activated bonding site comprises a first clean metal and the second surface activated bonding site comprises a second clean metal, and
wherein the first surface activated bonding site is coupled to the second surface activated bonding site such that respective metal atoms of the first activated surface activated bonding site are diffused into the second surface activated bonding site and respective metal atoms of the second activated surface activated bonding site are diffused into the first surface activated bonding site.
2. The apparatus according to claim 1 , further comprising:
an integrated circuit package substrate coupled to the plurality of silicon vias.
3. The apparatus according to claim 2 , further comprising:
a plurality of wirebonds coupled to the integrated circuit package substrate and to the first integrated circuit die.
4. A method comprising:
fabricating a first integrated circuit die including a plurality of silicon vias and a first surface activated bonding site;
fabricating a second integrated circuit die including a second surface activated bonding site; and
coupling the first surface activated bonding site to the second surface activated bonding site,
wherein the first surface activated bonding site is coupled to the second surface activated bonding site such that respective metal atoms of the first activated surface activated bonding site are diffused into the second surface activated bonding site and respective metal atoms of the second activated surface activated bonding site are diffused into the first surface activated bonding site.
5. The method according to claim 4 , further comprising:
coupling the plurality of silicon vias to an integrated circuit package substrate.
6. The method according to claim 5 , further comprising:
coupling a plurality of wirebonds to the integrated circuit package substrate and to the first integrated circuit die.
7. A system comprising:
a microprocessor die comprising a plurality of silicon vias and a first surface activated bonding site coupled to the plurality of silicon vias;
a chipset die comprising a second surface activated bonding site coupled to the first surface activated bonding site; and
a double data rate memory in communication with the chipset die, wherein the first surface activated bonding site comprises a first clean metal and the second surface activated bonding site comprises a second clean metal, and
wherein the first surface activated bonding site is coupled to the second surface activated bonding site such that respective metal atoms of the first activated surface activated bonding site are diffused into the second surface activated bonding site and respective metal atoms of the second activated surface activated bonding site are diffused into the first surface activated bonding site.
8. The system according to claim 7 , further comprising:
an integrated circuit package substrate coupled to the plurality of silicon vias.
9. The system according to claim 8 , further comprising:
a plurality of wirebonds coupled to the integrated circuit package substrate and to the first integrated circuit die.