Contact techniques and configurations for reducing parasitic resistance in nanowire transistors
View Patent ↗Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nanowire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor.
1. A method, comprising:
providing a semiconductor substrate;
depositing an isolation layer on the semiconductor substrate;
depositing a channel layer on the isolation layer, the channel layer to provide a channel for a transistor;
forming a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, material of the channel layer and to provide a source terminal or drain terminal for the transistor; and
depositing an epitaxial film on and epitaxially coupled with the channel layer, the epitaxial film surrounding, in the at least one planar dimension, material of the channel layer and being disposed between the material of the channel layer and material of the contact, wherein the material of the channel layer includes N-type or P-type semiconductor material and the epitaxial film includes a group III-V semiconductor material and has a thickness between 50 Angstroms and 1000 Angstroms.
2. The method of claim 1 , wherein the at least one planar dimension is substantially perpendicular to a planar surface of the semiconductor substrate upon which the transistor is formed.
3. The method of claim 1 , further comprising:
depositing a buffer layer on the semiconductor substrate, wherein the buffer layer is disposed between the semiconductor substrate and the isolation layer.
4. The method of claim 1 , wherein depositing the channel layer comprises epitaxially depositing the channel layer on the isolation layer.
5. The method of claim 4 , wherein forming the contact comprises:
selectively removing material of the isolation layer using an etch process; and
depositing a metal to replace the selectively removed material of the isolation layer to form the contact.
6. The method of claim 5 , wherein forming the contact further comprises:
epitaxially depositing the epitaxial film on the channel layer prior to depositing the metal to form the contact.
7. The method of claim 1 , wherein:
the epitaxial film includes a P-type material;
the material of the channel layer includes germanium (Ge) nanowire material; and
the isolation layer includes silicon germanium (SiGe).
8. The method of claim 1 , wherein the isolation layer is a first isolation layer and the channel layer is a first channel layer, the method further comprising:
depositing a second isolation layer on the first channel layer; and
depositing a second channel layer on the second isolation layer, wherein the contact is coupled with the second channel layer and configured to surround, in the at least one planar dimension, material of the second channel layer.
9. The method of claim 8 , wherein the contact is a source terminal, the method further comprising:
forming a drain terminal coupled with the first channel layer and the second channel layer, the drain terminal being configured to surround, in the at least one planar dimension, material of the first channel layer and material of the second channel layer; and
forming a gate coupled with the first channel layer and the second channel layer, the gate being disposed between the source terminal and the drain terminal and configured to control current flow of the transistor between the source terminal and the drain terminal.
10. The method of claim 8 , further comprising:
depositing an interlayer dielectric (ILD) on the second channel layer.