Autonomously controlling a buffer of a processor
In an embodiment, an apparatus includes an input/output (I/O) buffer to couple a logic unit to another device coupled via a pad, and a logic coupled to the I/O buffer to detect a value on the pad and to control the I/O buffer to provide the value to the pad, responsive to entry into an architectural state. Other embodiments are described and claimed.
1. An apparatus comprising:
an input/output (I/O) buffer;
a pad; and
a control circuit to:
determine a particular configuration of a plurality of configurations associated with the pad, the plurality of configurations comprising a plurality of architectural states and a plurality of directions, the plurality of architectural states comprising at least a reset de-assertion state and a power-good assertion state, and the plurality of directions comprising a transmit direction and a receive direction;
sample a state on the pad associated with the particular configuration of the pad; and
control the I/O buffer to maintain the sampled state at the pad while the pad is in the particular configuration.
2. The apparatus of claim 1 , the control circuit to:
sample the state on the pad in response to a first entry into the particular configuration of the pad.
3. The apparatus of claim 2 , the control circuit to:
control the I/O buffer to maintain the sampled state at the pad in response to a second entry into the particular configuration of the pad.
4. The apparatus of claim 1 , the control circuit to:
store an indication of the sampled state in a configuration storage.
5. The apparatus of claim 4 , the control circuit to:
control the I/O buffer to maintain the sampled state at the pad using the stored indication of the sampled state.
6. The apparatus of claim 4 , the control circuit to:
store the indication of the sampled state in the configuration storage in response to a determination that an override indicator is not active.
7. The apparatus of claim 1 , the control circuit to:
place the pad into a tri-state prior to sampling the state on the pad.
8. A processor formed in an integrated circuit (IC), the processor including:
at least one processing engine to execute instructions;
a pad;
an input/output (I/O) buffer; and
a controller to:
determine a particular configuration of a plurality of configurations associated with the pad, the plurality of configurations comprising a plurality of architectural states and a plurality of directions, the plurality of architectural states comprising at least a reset de-assertion state and a power-good assertion state, and the plurality of directions comprising a transmit direction and a receive direction;
sample a state on the pad associated with the particular configuration of the pad; and
control the I/O buffer to maintain the sampled state at the pad while the pad is in the particular configuration.
9. The processor of claim 8 , the control circuit to:
sample the state on the pad in response to a first entry into the particular configuration of the pad.
10. The processor of claim 9 , the control circuit to:
control the I/O buffer to maintain the sampled state at the pad in response to a second entry into the particular configuration of the pad.
11. The processor of claim 8 , the control circuit to:
store an indication of the sampled state in a configuration storage.
12. The processor of claim 11 , the control circuit to:
control the I/O buffer to maintain the sampled state at the pad using the stored indication of the sampled state.
13. The processor of claim 11 , the control circuit to:
store the indication of the sampled state in the configuration storage in response to a determination that an override indicator is not active.
14. A method comprising:
determining, by a control circuit, a particular configuration of a plurality of configurations associated with a pad of an apparatus, the plurality of configurations comprising a plurality of architectural states and a plurality of directions, the plurality of architectural states comprising at least a reset de-assertion state and a power-good assertion state, and the plurality of directions comprising a transmit direction and a receive direction;
sampling, by the control circuit, a state on the pad associated with the particular configuration of the pad; and
controlling, by the control circuit, an input/output (I/O) buffer to maintain the sampled state at the pad while the pad is in the particular configuration.
15. The method of claim 14 , comprising:
sampling the state on the pad in response to a first entry into the particular configuration of the pad.
16. The method of claim 15 , comprising:
controlling the I/O buffer to maintain the sampled state at the pad in response to a second entry into the particular configuration of the pad.
17. The method of claim 14 , comprising:
storing an indication of the sampled state in a configuration storage.
18. The method of claim 17 , comprising:
controlling the I/O buffer to maintain the sampled state at the pad using the stored indication of the sampled state.
19. The method of claim 17 , comprising:
determining whether an override indicator is active; and
storing the indication of the sampled state in the configuration storage in response to a determination that the override indicator is not active.
20. The method of claim 14 , comprising:
placing the pad into a tri-state prior to sampling the state on the pad.